New Touchscreen function for Guren project.
Touchscreen panel: HKO RB116AS01-2,
and set TOUCHSCREEN_FTSC1000 to value "3".
BUG=b:391281767
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: Icfe5f57c69d1bd98e0852a1aa3baed8c1444e4d9
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87238
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for
Panther Lake SoC has been removed.
Panther Lake platforms inherently enable display across all boot
modes (normal, developer, recovery) when vboot is active.
Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY`
becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY`
is enabled due to the selection of `BMP_LOGO` for ChromeOS
devices.
TEST=Able to perform ec sync without any additional reboots.
Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `display_init_required` function for vboot now mandates that either
`CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or
`CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled.
If neither of these Kconfig options is set when `CONFIG_VBOOT` is
enabled, the code will now trigger `dead_code()`. This enforces the
requirement that display initialization is explicitly requested or
always enabled when vboot is active, aligning with the intended usage
of `VB2_CONTEXT_DISPLAY_INIT`.
TEST=Able to build google/fatcat.
Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the initialization logic for the optional QUPv3 wrapper 2.
Add a runtime check of the `QUP_WRAP2_BASE` macro's value within
`qupv3_fw_init`.
This approach simplifies the QUP wrapper 2 initialization, making the
code flow depend directly on whether a valid base address is defined
for the target SoC.
To facilitate this, explicitly define `QUP_WRAP2_BASE` as 0 (acting as
a dummy entry) for SoCs like sc7180 and sc7280 which do not include
this hardware block. The `if (QUP_WRAP2_BASE)` check will correctly
evaluate to false for these platforms, skipping the initialization.
Platforms that do have QUP wrapper 2 should define its non-zero base
address.
TEST=Able to build google/herobine.
Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a conditional bypass for ME state setting,
potentially reducing CBFS traversal time when searching for the
`option/me_state` file.
TEST=Able to build and boot google/fatcat.
Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87266
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch increases the default heap size from 1MB to 2MB (0x200000) to
accommodate rendering high-quality firmware splash BMP logos.
The previous 1MB heap size might be insufficient for larger, more
detailed OEM logos, potentially leading to memory exhaustion during the
splash screen display.
TEST=Able to render an OEM logo size ~512KB w/o any corruption.
Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87265
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD SoC from family 17h share common cpu init code.
Move those to common/block/cpu/noncar/cpu.c
TEST=Build for glinda SoC & check for boot.
Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To allow adding more scripts to the util/mtkheader folder, rename it to
util/mediatek. Also update description.md and regenerate
Documentation/util.md and util/README.md by util_readme.sh.
Change-Id: Ibc6ef9dddc541d2dd471898af431cadde231edca
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
As CB:71757 [1] updates Documentation/util.md and util/README.md
manually without modifying util/intelp2m/description.md, we port the
description changes back to that file.
[1] commit da54bd60af ("Documentation: Update information about
intelp2m")
Change-Id: I3d3f87517c445d650e9cea61448b28d005d46737
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87224
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update SoundWire driver to support ALC712 audio codec.
reference datasheet: Realtek ALC712-VB-CG Rev. 0.24
BUG=b:378629979
TEST=emerge-fatcat coreboot
A sound can be heard from the speaker,
the test instructions are as follows:
amixer -c 0 cset name='rt712 OT23 L Switch' on
amixer -c 0 cset name=''rt712 OT23 R Switch' on
amixer -c 0 cset name='rt1320-1 OT23 L Switch' on
amixer -c 0 cset name='rt1320-1 OT23 R Switch' on
amixer -c 0 cset name='Speaker Switch' on
speaker-test -D hw:0,2 -c 2 -t sine -f 440
Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Previously only tested on server platforms - it wasn't working correctly
on consumer platforms due to missing boolean.
This patch fixes it, which makes resource allocator use uint64 instead
of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now
work correctly with ReBAR enabled, and correctly initialize the
framebuffer in payload (i.e EDK2) after initializing the OpROMs.
Example of issue caused by resource allocator using uint32 (Intel Arc
A580):
[ERROR] Resource didn't fit!!!
[ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned
[ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned
(Followed by Linux reporting that BAR space was limited to 256MB, which
severely hindered the performance).
TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD
Radeon RX7800XT.
Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The board uses GPP_G19 as GPIO interrupt for SPI dTPM. The pad
is already configured as APIC interrupt, so simply define the
TPM_PIRQ to GPP_G19_IRQ, which is 0x6B for Elkhart Lake.
TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not
complain on TPM interrupt not working. Check Windows Device
Manager does not report any problem with TPM and its resources.
Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87051
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.
BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log :
000000013fff0000-000000013fffffff: RESERVED
000000023fff0000-000000023fffffff: RESERVED
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This doesn't change any text - it just reformats the existing document.
- reflow paragraphs to 72 characters
- Put examples inside pre-formatted text blocks
- Adds spacing before section markers
Change-Id: I83925a4469e264da5887334e2584466cef089503
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Add USB host function support.
BUG=b:379008996
BRANCH=none
TEST=boot to kernel successfully from USB drive
Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com>
Change-Id: I3f77d116033338f979d14ce34ddf03e00d024e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To promote code reuse and maintainability, this commit moves the DRAMC
parameter function declarations to the common folder.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The configuration method of the reserved DRAM buffer used for HW TX
TRACING on MT8196 is also applicable to other SoCs, such as MT8189.
To facilitate reuse, we move the relevant files to the common directory.
BUG=b:379008996
BRANCH=none
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED
Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add DRAM calibration support for mt8189. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h.
The common emi.c can be reused for MT8189 as well, so remove the
duplicate mt8189/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.
BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Meliks cannot use Samsung K3KL8L80DM-MGCU memory part since Twin Lake
platform can only support memory parts that support 8B mode but this
part doesn't support it.
So we would replace the usage of RAMID 2 (b'0010) with the SPD for this
part which supports 8B mode.
- Samsung K3KL8L80CM-MGCT
BUG=b:402600450
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot
Change-Id: I7c05b79ca018f68260e71d4f749ecb8573987358
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87002
Reviewed-by: NyeonWoo Kim
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
FMAP should not contain information about the memory map.
Done with the following command:
"find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;"
for AMD:
All addresses that amdfwtool expects as command line parameter have the
ADDR_REL_BIOS (flash address) address_mode setting. One exception is
the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks
if memory or flash addresses are passed and converts accordingly. So
changing the address from memory -> flash doesn't matter for the
resulting binary.
Since commit 41a162b7a8 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV
address as offset") and therefore since phoenix SOC, APOB_NV is passed
as flash offset. But before that the memory ABL always assumed a MMIO
address (no matter the address_mode) so we need to add a little quirk
for that.
tested: boot glinda based mainboard and also check that memory training
is still cached successfully in APOB_NV.
Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch moves eSOL enablement from the SoC level to the mainboard level. This gives the mainboard the option to not use eSOL if it's not supported.
The FSP_UGOP_EARLY_SIGN_OF_LIFE Kconfig option is now enabled for the Fatcat and Felino boards.
This option was previously enabled at the SoC level for Pantherlake,
but is now being enabled specifically for these mainboards.
BUG=b:400550435
TEST=Build the Fatcat and Felino targets. Verify that the eSOL works
fine.
Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87236
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Uses fw_config to check if barrel jack PSU is configured. If
`PSU_BJ` is selected, checks hardware presence via
`google_chromeec_is_barrel_charger_present()`.
Allows 'fatcat' to adapt based on configured power source.
Includes:
- Adds `variant.c` to ramstage build in `Makefile.mk`.
- Adds `PSU` field (`PSU_USBC`: 0, `PSU_BJ`: 1) to `overridetree.cb`.
- Includes `ec.h` in `variant.c`.
TEST=Boot time savings ~62ms on google/fatcat with PSU=0 (USB-C).
Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a weak function
`variant_is_barrel_charger_present()` to allow individual Fatcat
variants to specify if they support power-on via a barrel jack.
The default implementation of this function returns `false`,
reflecting the fact that most Chromebook devices within the Fatcat
family primarily use USB-C for power.
The `baseboard_devtree_update()` function is updated to use this
variant-specific check instead of directly calling
`google_chromeec_is_barrel_charger_present()` and checking the board
model. This allows for more flexibility in handling barrel jack
presence across different Fatcat variants.
This change enables specific variants that do support barrel jack
power to override the weak function and return `true`, allowing the
system to behave accordingly (e.g., skipping power optimization when
booting with a barrel charger).
TEST=Able to build and boot google/fatcat.
Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87183
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit restructures the GPIO configuration for google/fatcat
devices as below.
- Phase 1: GPIO configuration at pre-memory phase. This phase
configures essential GPIOs like WWAN and storage power sequencing,
This aligns with the initial power-up requirements of
these critical components.
- Phase 2: This phase handles GPIO configurations for various
peripherals like storage type, audio codec, WiFi, cellular interface
(post initial power sequence), SD card slot, touchpad, touchscreen,
ISH, PEG/x4 slot wake disable, and fingerprint enable/disable based
early in post-memory phase (before MPInit).
This phased approach:
- Improves power sequencing by ordering GPIO configuration for proper
IP power enablement.
- Optimizes boot time by performing more GPIO configuration before
MPInit and FSP-S, allowing earlier IP stabilization and potentially
saving ~20ms during device setup and PCIe scan.
`baseboard_devtree_update` remains in `mainboard_init` for baseboard-
specific device tree updates.
TEST=Boot time improved by ~20ms on google/fatcat.
Before:
70:device setup done 1,339,599 (95,023)
After:
70:device setup done 1,319,613 (72,381)
Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87191
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Must have been accidentally happened when copying phoenix to glinda.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I78996cd35085c7649c4952d9b121957c8cedd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86865
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Change the SSD Enable GPIO to PLTRST, as having it configure to DEEP,
renders the SSD inaccessible on S3 exit as it conflicts with the RTD3
driver.
Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87213
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New Touchscreen function for Guren360 project.
Touchscreen panel of MUTTO A153728S1Y(11')
/K&D KD116N37-30TE-A002(11')/MUTTO B153797S1Y(12') are the
same IC controller for ILITEK device, and set TOUCHSCREEN_ILIT2901
to value "2".
BUG=b:406168542
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I3435a8852b1fdb897d5f89c580b5f9bfca03dd8e
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
The code currently unconditionally flushes or invalidates the entire
cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector
for APs and after loading SMM handlers.
This commit modifies this behavior to only perform these cache
operations if the CPU does *not* support self-snooping.
Self-snooping CPUs can maintain cache coherency within the core/
complex more efficiently. CPU with self-snoop enabled does not
necessarily need to perform wbinvd to ensure data written to the
cache is reflected in main memory. Self-snooping CPUs employ a
write-back caching policy, combined with a cache coherence protocol,
to manage data writes and ensure consistency between cache and main
memory.
When the BSP writes the SIPI vector or SMM handlers to memory, other
units within the same CPU that might be caching these regions should
be aware of the updates through the self-snooping mechanism. A full
cache flush or invalidate to ensure cache contains reaches to main
memory might be unnecessary and could negatively impact performance.
By conditionally performing these cache operations based on
`self_snooping_supported()`, we can optimize the boot process for CPUs
that have advanced cache coherency features while maintaining correct
behavior on older or simpler CPUs.
TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce
boot time by ~19-25ms.
Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87182
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The system was failing to boot to the OS when the SD FW config was
set to NONE. This was because the X1 PCIe slot power enable (GPP_A08)
was being configured in `pre_mem_x1slot_pads` only if the SD FW config
was not NONE.
This commit moves the configuration of GPP_A08 to the
`romstage_gpio_table` and sets it to an initial low state. This ensures
that the X1 PCIe slot power is correctly initialized early in the boot
process, regardless of the SD FW config.
The `pre_mem_x1slot_pads` array and its conditional configuration in
`fw_config_configure_pre_mem_gpio` have been removed as they are no
longer needed.
TEST=Able to boot google/fatcat w/ CBI 0x5c9014 (i.e. SD_NONE)
Change-Id: I0f2a2540de30294c30c4f5182dab326a54b4583e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87154
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kconfig options `USE_INTEL_FSP_MP_INIT` and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` are mutually
exclusive ways for the FSP to handle MP initialization.
This commit updates the `default` condition for
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` to `y if
!USE_INTEL_FSP_MP_INIT`. This ensures that if
`USE_INTEL_FSP_MP_INIT` is enabled,
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` will default
to disabled, preventing potential conflicts in MP initialization.
The explicit `depends on
!USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI`
on `USE_INTEL_FSP_MP_INIT` is no longer strictly necessary due to
this change in the default value, but it is kept for clarity and
to explicitly state the mutual exclusivity.
TEST=Able to choose USE_INTEL_FSP_MP_INIT Kconfig for
google/fatcat.
Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87161
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.
Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.
Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.
The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."
Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The line length limit in the commit messages is 72 characters, not 75,
so fix the value in the documentation. The 72 characters also matches
what checkpatch checks for.
Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since we need to support both MBVR (MotherBoard Voltage Regulator) and
FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT
setting is initially set to FIVR. This causes MBVR boards to have two
voltage sources, potentially triggering OVP and leading to reboots
during the boot process.
The current build's main source is MBVR, so we want to use fw_config
to dynamically adjust MFIT and MBVR with the current phase devices to
ensure consistency in client devices settings.
Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30
(VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a
temporary workaround for the current phase. In the next phase, we will
choose a specific setting for implementation. If there are any concerns,
we use the board ID to restrict it.
BUG=b:404126972
TEST=boot to ChromeOS
Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
These were previously removed, but doing so, slowed down the
brightness keys to approx. 3 seconds.
Re-add them to make them instant.
Change-Id: I1256b57192d2f8987bb476cbcc7fd7e81f314d6d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87200
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These were previously removed, but doing so, slowed down the
brightness keys to approx. 3 seconds.
Re-add them to make them instant.
Change-Id: I3af197cd995bd947c6e72bf5593fc966c85c3e3a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces a new timestamp `TS_DEVICE_INIT_CHIPS` to
specifically mark the start of the `dev_initialize_chips()` function.
Previously, the `TS_DEVICE_ENUMERATE` timestamp was incorrectly
associated with the `bs_dev_init_chips` function.
This patch corrects this by:
- Adding the `TS_DEVICE_INIT_CHIPS` enum and name definition.
- Updating `bs_dev_init_chips` in `src/lib/hardwaremain.c` to use
`TS_DEVICE_INIT_CHIPS`.
- Moving the `TS_DEVICE_ENUMERATE` timestamp addition to the
`bs_dev_enumerate` function where device enumeration actually begins.
This change provides a more accurate and meaningful timestamp for the
early chipset initialization phase.
TEST=Able to build and boot google/fatcat.
```
971:loading FSP-S 836,277 (10,658)
17:starting LZ4 decompress (ignore for x86) 847,297 (11,019)
18:finished LZ4 decompress (ignore for x86) 847,376 (79)
30:early chipset initialization 854,579 (7,203)
17:starting LZ4 decompress (ignore for x86) 863,483 (8,903)
18:finished LZ4 decompress (ignore for x86) 863,490 (6)
17:starting LZ4 decompress (ignore for x86) 875,196 (11,705)
18:finished LZ4 decompress (ignore for x86) 875,237 (41)
954:calling FspSiliconInit 875,344 (107)
955:returning from FspSiliconInit 942,740 (67,396)
962:calling FspMultiPhaseSiInit 942,744 (4)
963:returning from FspMultiPhaseSiInit 1,081,355 (138,610)
31:device enumeration 1,081,708 (352)
40:device configuration 1,085,721 (4,013)
50:device enable 1,091,517 (5,795)
```
Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
New WFC function for Guren360 project.
ID of Vendor and Product for AZWAVE/AM-3BA5533-B module are 13d3:5533.
1. Add WFC fw_config setting
2. Used USB2 Port7 for WFC
BUG=b:406164678
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Verified with local build bios via command lsusb
for 13d3:5533 and SSFC WFC enable
Change-Id: Ia2ab019fe76c503cc669ebf4aa8b3d7ae72269c1
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
