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mb/var/uldrenite: Configure descriptor for either MBVR or FIVR

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Since we need to support both MBVR (MotherBoard Voltage Regulator) and
FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT
setting is initially set to FIVR. This causes MBVR boards to have two
voltage sources, potentially triggering OVP and leading to reboots
during the boot process.

The current build's main source is MBVR, so we want to use fw_config
to dynamically adjust MFIT and MBVR with the current phase devices to
ensure consistency in client devices settings.

Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30
(VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a
temporary workaround for the current phase. In the next phase, we will
choose a specific setting for implementation. If there are any concerns,
we use the board ID to restrict it.

BUG=b:404126972
TEST=boot to ChromeOS

Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
John Su 2025-03-28 10:21:49 +08:00 • committed by Jérémy Compostella
commit 05ec649338
3 changed files with 31 additions and 0 deletions
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1
src/mainboard/google/brya/Kconfig
View file

@ -669,6 +669,7 @@ config BOARD_GOOGLE_ULDREN
select INTEL_GMA_HAVE_VBT
config BOARD_GOOGLE_ULDRENITE
select ALDERLAKE_CONFIGURE_DESCRIPTOR
select BOARD_GOOGLE_BASEBOARD_TRULO
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_WWAN_FM350GL

1
src/mainboard/google/brya/variants/uldrenite/Makefile.mk
View file

@ -1,6 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
bootblock-y += variant.c
romstage-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c

29
src/mainboard/google/brya/variants/uldrenite/variant.c
View file

@ -2,10 +2,12 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <console/console.h>
#include <delay.h>
#include <fw_config.h>
#include <sar.h>
#include <soc/bootblock.h>
const char *get_wifi_sar_cbfs_filename(void)
{
@ -75,3 +77,30 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
printk(BIOS_INFO, "Configured External FIVR\n");
}
}
void variant_update_descriptor(void)
{
uint32_t board_version = board_id();
/* b/404126972: Only this phase has M/B with both FIVR and MBVR. */
if (board_version != 1)
return;
/* VccanaVrLocation = "VCCANA is CPU FIVR" */
struct descriptor_byte fivr_bytes[] = {
{ 0xc33, 0x32 }
};
/* VccanaVrLocation = "VCCANA is Platform VR" */
struct descriptor_byte mbvr_bytes[] = {
{ 0xc33, 0x72 }
};
if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
printk(BIOS_INFO, "Configuring descriptor for MBVR\n");
configure_descriptor(mbvr_bytes, ARRAY_SIZE(mbvr_bytes));
} else {
printk(BIOS_INFO, "Configuring descriptor for FIVR\n");
configure_descriptor(fivr_bytes, ARRAY_SIZE(fivr_bytes));
}
}