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mb/google/fatcat/variants/fatcat: Refactor X1 PCIe power enable GPIO

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The system was failing to boot to the OS when the SD FW config was
set to NONE. This was because the X1 PCIe slot power enable (GPP_A08)
was being configured in `pre_mem_x1slot_pads` only if the SD FW config
was not NONE.

This commit moves the configuration of GPP_A08 to the
`romstage_gpio_table` and sets it to an initial low state. This ensures
that the X1 PCIe slot power is correctly initialized early in the boot
process, regardless of the SD FW config.

The `pre_mem_x1slot_pads` array and its conditional configuration in
`fw_config_configure_pre_mem_gpio` have been removed as they are no
longer needed.

TEST=Able to boot google/fatcat w/ CBI 0x5c9014 (i.e. SD_NONE)

Change-Id: I0f2a2540de30294c30c4f5182dab326a54b4583e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87154
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2025-04-04 15:20:26 +05:30
commit 7887417b4e
2 changed files with 2 additions and 7 deletions
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7
src/mainboard/google/fatcat/variants/fatcat/fw_config.c
View file

@ -165,10 +165,6 @@ static const struct pad_config audio_disable_pads[] = {
PAD_NC(GPP_D17, NONE),
};
static const struct pad_config pre_mem_x1slot_pads[] = {
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
PAD_CFG_GPO(GPP_A08, 0, PLTRST),
};
static const struct pad_config x1slot_pads[] = {
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
@ -566,9 +562,6 @@ void fw_config_configure_pre_mem_gpio(void)
GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads);
}
if (!fw_config_probe(FW_CONFIG(SD, SD_NONE)))
GPIO_CONFIGURE_PADS(pre_mem_x1slot_pads);
/*
* NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM
* FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V

2
src/mainboard/google/fatcat/variants/fatcat/gpio.c
View file

@ -390,6 +390,8 @@ static const struct pad_config early_gpio_table[] = {
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
PAD_CFG_GPO(GPP_A08, 0, PLTRST),
/* GPP_C00: GPP_C0_SMBCLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: GPP_C1_SMBDATA */