The changes focus on offering power state current thresholds, Thermal
Design Current (TDC) mode settings, and P-core and E-core hysteresis time
windows to support acoustic noise mitigation.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I949dd6a5c6bf575415ee62dcd0d0eda369ef29fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89330
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The changes focus on offering power state current thresholds and Thermal
Design Current (TDC) mode settings.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I25b6b9d2bf19ade51e39db06298ffaef98a7897e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88043
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Details:
- First set files to compile google/ocelot mainboard w.r.t. WCL FSP
3266_02.
- Change file path for the FSP_HEADER_PATH for WildacatLake.
BUG=b:431683053
TEST=Build Ocelot without any errors.
Change-Id: Iec31b0055bc145d795adef6723511ac07f83406b
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88433
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the existing TWL FSP headers, which were copied from ADL-N,
with the actual TWL headers.
TEST=starlabs byte_twl passes abuild w/o using IOT FSP.
Change-Id: I5c2836e81dee47dee73b14ce02f7bb8d0e846135
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit exposes the Thermal Design Current (TDC) limit in the
FSP_M_CONFIG structure. The TDC Current Limit is defined in 1/8A
increments. This allows for more precise control over the thermal design
current settings, enhancing power management capabilities.
Change-Id: Ie35611d5cdc14114542ac1a61611aa333c4bb1c9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
When a ChromeOS device has `SPLASH_SCREEN_FOOTER` Kconfig enabled and
provides a logo path for an OEM-defined boot splash logo in the footer,
it indicates that the device doesn't need to render
`cb_plus_logo.bmp` logo (hence, avoid packing this bitmap for platforms
that select `SPLASH_SCREEN_FOOTER` Kconfig).
In such cases, only the main OEM logo should be displayed at the center
of the splash screen along with custom bitmap at footer of the splash
screen.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie5085babe2f8373058ce1aa18b7071260f2aef7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88099
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update header files for FSP for Panther Lake platform to version
3182.01, previous version being 3144.01.
Changes include:
- Update FspmUpd.h
- Add PprRetryLimit and Use1p5ReadPostamble variable
BUG=b:421287370
TEST=Able to build google/fatcat with the partial header changes
Change-Id: I14e8c3c8751ae6aa0718d0015a1611ced6a2cdd4
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87879
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use POSTPONE_SPI_ACCESS to handle elog data later boot phase to avoid
flash access delay by other boot controllers.
Intel has pre-CPU boot controllers (e.g. CSE) which load non-CPU
firmwares. Boot-critical firmwares are loaded before CPU reset and
non-boot-critical firmwares are loaded during CPU boot. If another
controller accesses SPI to load firmwares, reading SPI by CPU is ok,
but writing to SPI for saving elog data can take ~32ms sometimes.
Saving elog data usually takes less than 1ms.
There are three elog handling sequences that need to move together
under the Kconfig:
- Soc folder
- Elog driver folder
- ChromeOS folder
Before this change, sometimes it delays like below:
BS: callback (0x7386d428) @ src/soc/intel/pantherlake/elog.c:216 (32 ms)
After this change, the delay is less than 1 ms:
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms)
TEST
1. Enable DEBUG_BOOT_STATE
2. Check time
BS: callback (0x7386d3e8) @ src/soc/intel/pantherlake/elog.c:213 (0 ms))
Change-Id: I3f5e7acf5204e213179664d0d77151d415d00896
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This change moves pvmfw cbmem implementation to chromeos directory and
under CHROMEOS kconfig. The kconfigs have been renamed accordingly and
with this change CHROMEOS_PVMFW_CBMEM is enabled by default for
CHROMEOS.
BUG=b:410735713
TEST=The build with CONFIG_CHROMEOS=y allocates buffer for pvmfw, the
depthcharge adds the location and size of the buffer to the kernel
command line
Change-Id: I024f21ceee1334ebd7ae9bf1b897ad670ddc9ef9
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87763
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update header files for FSP for Panther Lake platform to version
3144_01, with the previous version being 3071_00.
Changes include:
- Update UPD Offset in FspmUpd.h and FspsUpd.h.
- Update MemInfoHob.h:
- Update MEMORY_INFO_DATA_HOB, child structures and their data for
SMBIOS type 16/17 design change.
- Add new variable PprFailingChannelBitMask to
MEMORY_INFO_DATA_HOB.
- Update soc/intel/pantherlake/romstage/romstage.c: Refactor coreboot
to match MEMORY_INFO_DATA_HOB data structure.
BUG=b:414734316
TEST=Able to build google/fatcat. Verify that the updates to
MEMORY_INFO_DATA_HOB and its child structures for SMBIOS type 16/17
design changes are correctly integrated from FSP 3144_01 onwards.
Change-Id: I054e419ef23ada67347750e7a68014c2bb112199
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The size is different depending on the SOC in question.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iecd3d8b41c530c1c71f659facaa5a75659930ea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87584
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The missing header was added to the Intel FSP repo (commit 43f7092a6156
("IoT RPL-S MR2 (4415_02) FSP"), so remove it from vendorcode as it is
no longer needed.
This reverts commit c651a27b53 ("vc/intel/fsp2_0: Add a copy of
ADL-S IOT FSP MemInfoHob.h for RPL-S IOT") which was only meant to
be a temporary fix.
Change-Id: I1e7a35f62677e39fda47f61c6c49bec0b415c2a5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Add an allocation of an empty buffer for the Android protected virtual
machine firmware within cbmem. The buffer will be filled by the payload
and the purpose is to just reserve the memory. cbmem is used to make
sure that the region won't overlap with other reserved regions
or device regions.
BUG=b:354045389
BUG=b:359340876
TEST=depthcharge receives the buffer through lib_sysinfo
BRANCH=main
Change-Id: I48efc033ac0f5fbfcf3a52fabf40be016cd4c6f7
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This reverts commit 07dd73c921.
Jasperlake FSP does not properly support the crashlog feature, and
enabling it results in several issues (increased boot time, issues
with USB device detection).
Change-Id: I5598b40321b3ca15a48ac6eff64a85323d55939d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ is still needed due to
Intel FSP repo does not ship all header files.
TEST=Build and boot on intel/archercity CRB
Change-Id: I778d3535c273dff653330518653bdefcb45e66f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors low-battery user notification logic (Kconfig,
APIs to check if low-battery rendering is required, low-battery
shutdown is required) outside FSP driver code to ensure in future
non-FSP platforms might still be able to leverage this feature/logics
to render the low-battery indicator icon during boot.
Specifically, it:
- Moves Kconfig options related to low-battery notifications from
drivers/intel/fsp to lib/
- Relocates the low-battery check and shutdown APIs drivers/intel/fsp
to bootsplash.h
* Adjusts the vendor driver to utilize the new APIs for low-battery
rendering decisions.
* Drop the unwanted header file "fsp/api.h" from bmp_logo.c
This change avoids tight coupling of low-battery functionality to FSP,
promoting code reusability across platforms.
BUG=b:400738815
TEST=Able to build and boot google/brox.
Change-Id: Iaa730dac2bb4866183408b6390221f0bb8411a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Refactor the vendorcode openSIL memory map code and move all common
calls that do not require any openSIL headers to the driver. Improve
the legibility of the logic to return memory hole type string.
Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update header files for FSP for Panther Lake platform to version
3015_00, with the previous version being 2454_00.
Changes include:
- Updating UPD Offset in FspmUpd.h and FspsUpd.h
- Adding Sign-of-Life related UPDs in FspmUpd.h
- Adding VMD related UPDs in FspsUpd.h
BUG=b:394189627
TEST=Able to build google/fatcat.
Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86297
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit implements `platform_is_low_battery_shutdown_needed` and
callback for ChromeOS.
- platform_is_low_battery_shutdown_needed: API to check if low battery
shutdown is needed.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I119f80a45c045a6095cae98f179c755a2e948e9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit introduces a new macro, cbfs_add_bmp_file, to the ChromeOS
vendor code Makefile. The macro simplifies the process of adding BMP
files to the CBFS (coreboot Filesystem) by encapsulating the
repetitive tasks of specifying file attributes such as file path,
type, and compression flag.
TEST:Both 'cb_logo.bmp' and 'cb_plus_logo.bmp' files are included with
the same properties, within the coreboot firmware image.
Change-Id: I827451da79931c09768965c3ad071ecdd918d367
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Define the generic cbmem_top_chipset() in the driver code, which will
invoke a SoC-specific vendorcode openSIL call to retrieve the low
usable DRAM address.
Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Refactor to factor out and route ACPI calls through the openSIL driver
interface to separate main SoC code from vendorcode.
Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of
the address space. Most of the PCI BARs reside in high MMIO, not
reachable by x86_32 coreboot.
Add support for x86_64 coreboot and confirm that all supported boards
are booting without errors. This is done by:
- converting all occurrences of VOID * to UINT32 to make sure that
FSP UPDs do not change when pointers are 8byte wide.
- Drop SetupStructPtr as it's unused within FSP and coreboot
TEST: Booted on ocp/tiogapass to Linux. No errors were observed.
Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Updates the structures to match the ones in the FSP.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0603f5da689b6738ea54305a665b150121bc520c
Original-signed-off-by: Satya SreenivasL <satya.sreenivasl@amd.com>
Original-reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Original-reviewed-by: Ritul Guru <ritul.bits@gmail.com>
Original-tested-by: Satya Sreenivas L <Satya.SreenivasL@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Refactor vendorcode MPIO configuration functions to be invoked from
the openSIL driver.
Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Fix the typo in the word "unknown", and add 1 to the timepoint enum to
print out 1, 2 and 3 instead of 0, 1 and 2.
Change-Id: I1308fd102490a89ff8b724509917180034d8d0c0
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Update header files for FSP for Meteor Lake platform to version 4122_21,
previous version being 3471_91.
FSPS:
1. Added UPD's ThcMode, ThcWakeOnTouch
2. Reserved bit changes
FSPM:
1 Added PchHdaSubSystemIds
BUG=b:329548127
TEST=Able to build and boot google/rex to ChromeOS.
Change-Id: I4a1164060f7e91f8fa4ada60421bf87fb17ad541
Signed-off-by: alokagar <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84656
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common
code fill in the SMBIOS type 17 entries for all slots and found DIMMs.
This also allows to build dimm.c unconditionally on all xeon_sp socs.
Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS.
Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drive Strength BRI Rsp Object provides information from the OEM
platforms if they have replaced the Bluetooth Radio Interface resistor
to overcome the potential STEP errors on their designs. Based on
configuration, CNV firmware shall adjust the BRI Rsp line drive
strength.
The bri_resistor_value is encoded as follow:
| Bit | Val | Description | Default |
|------+-----+---------------------------------------------+---------|
| 0 | 0 | Device FW default values | 1 |
| | 1 | Override device FW default values | |
| 3:1 | 0 | Reserved (shall be set to 0) | 0 |
| 7:4 | 0 | DSBR override values (only if bit 0 is set) | 0xf |
| 31:7 | 0 | Reserved (shall be set to 0) | 0 |
Possible values:
- 0xf1 (default): indicates that the resistor on board is 33 Ohm
- 0x0 or 0xb1: indicates that the resistor on board is 10 Ohm
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=DSBR methods are added to the wifi device and bluetooth companion
device and they return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e300
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85017
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature provides ability to provide Wi-Fi PHY filter
Configuration. A well-defined dedicated filter on particular platform
can be used to perform the maximum Wi-Fi performance.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=WPFC method is added to the wifi device and return the data
supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e270
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84948
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extended Bluetooth Regulatory Descriptor (EBRD) SAR/RFE are safety
regulations for limiting antenna radiation near human contact. EBRD
provides option to provide up to three sets of TX power limits and
power restrictions.
As the EBRD table is related to the revision 2 of the BRDS, this
commit also adds support for this new revision.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=EBRD method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e250
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84947
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature provides ability to set the Bluetooth Dual Mac Mode
setting.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BDMM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e240
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84946
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This feature provides ability to set the Bluetooth Ultra High
Band (UHB) settings per country. The bluetooth UHB country selection
is defined as follow (default is 0):
| Bit | Value | |
|-------+-------+---------------------------------------------------|
| 0 | 0 | No override; use BT device settings |
| | 1 | Force disable BT in all countries that are not |
| | | defined in the following bits |
| 1 | 0 | USA 6GHz BT disable |
| | 1 | 6GHz BT allowed in the USA (enabled only if the |
| | | device is certified to the USA) |
| 2 | 0 | Rest of the World 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Rest of the World (enabled |
| | | only if the device is certified to the rest |
| | | of the world) |
| 3 | 0 | EU countries 6GHz BT disable |
| | 1 | 6GHz BT allowed in the EU countries (enabled only |
| | | if the device is certified to the EU countries) |
| 4 | 0 | South Korea 6GHz BT disable |
| | 1 | 6GHz BT allowed in the South Korea (enabled only |
| | | if the device is certified to the South Korea) |
| 5 | 0 | Brazil 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Brazil (enabled only if |
| | | the device is certified to the Brazil) |
| 6 | 0 | Chile 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Chile (enabled only if the |
| | | device is certified to the Chile) |
| 7 | 0 | Japan 6GHz BT disable |
| | 1 | 6GHz BT allowed in Japan (enabled only if the |
| | | device is certified to Japan) |
| 8 | 0 | Canada 6GHz BT disable |
| | 1 | 6GHz BT allowed in Canada (enabled only if the |
| | | device is certified to Canada) |
| 9 | 0 | Morocco 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Morocco (enabled only if |
| | | the device is certified to the Morocco) |
| 10 | 0 | Mongolia 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Mongolia (enabled only if |
| | | the device is certified to the Mongolia) |
| 11 | 0 | Malaysia 6GHz BT disable |
| | 1 | 6GHz BT allowed in the Malaysia (enabled only if |
| | | the device is certified to the Malaysia) |
| 31:12 | 0 | Reserved Should set to zeros |
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BUCS method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e231
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This feature provides ability to provide dual chain setting.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BDCM method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e220
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84943
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This feature provides ability to identify non-LTE platform and disable
BiQuad Bypass filter logic in hardware for Bluetooth usecases reducing
device power consumption.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BBFB method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e213
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The ACPI BPAG method provide information to controls the antenna gain
method to be used per country.
The antenna gain mode is a bit field (0 - disabled, 1 -enabled)
defined as follow:
- Bit 0 - Antenna gain in EU
- Bit 1 - Antenna gain in China Mainland
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 9.2 specification.
BUG=b:346600091
TEST=BPAG method is added to the bluetooth companion device and return
the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e210
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Properly scan all logical stack when creating PCI domains.
Fixes PCI bus ranges being used on other stacks, since they look
unused, as not all stacks are checked.
Change-Id: I13c8b389a585dbccec182d3c98021f1d9d648b2c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Create a new config option to indicate that a board has Google Strauss
keyboard. The scan code for Fn key will be set to 94 if the new config
is selected.
Previously each board was setting the integer config option for Fn key
scan code which was not scalable. The new option is a bool and can be
easily selected by different boards.
BUG=none
TEST=Verify coreboot.config before and after this change.
Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85109
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is to add FspProducerDataHeader.h header file to support MRC
version Info in RPL.
BUG=b:281846937
TEST=Able to build and boot google/brox.
Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
