Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This is a legacy option that changed the charging frequency. It
is no longer needed as the "normal" frequency is faster and more
stable so remove it.
Change-Id: I73cf439d96d65f0be26595e42a4aedbc4388b850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. Add DB_1C_5G 8 on DB_USB overridetree.
2. Also disable LTE-related GPIOs based on fw_config when system
was DB_1C_5G.
BUG=b:445338278
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Check 5G LTE module detectable by command # mmcli -m a.
Change-Id: I3d525d9de151427d38485882117b59939b9da5c7
Signed-off-by: Joyce Ciou <Joyce_Ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89606
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG= b:435094908
TEST= verify headset jack works properly.
Change-Id: Ibd5271e496a9ca841498b17a5746e300f9557078
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89605
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add usb_repeater_spmi_init() and usb_repeater_spmi_tune() functions
for USB repeater internal to SMB2360 via SPMI configuration
during HS PHY initialization.
The usb_repeater_spmi_init() function enables Embedded USB2 control for
both SMB1 and SMB2 cores, while usb_repeater_spmi_tune() configures
optimal signal integrity parameters (IUSB2, USB2_SLEW, USB2_PREEM)
for reliable Type-C connectivity.
BUG=b:451814646
TEST=Verify USB2.0 (HS) works for C1 on Google/Bluey.
Without this CL -
USB2 key doesn't work for C1.
Verified HS1 functionality by turning on L14B from coreboot.
Before USB insertion:
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Added USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 00000e03 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Removed USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
Change-Id: I24e0af062fc7a6b5effd9317ec5c0b2d89fe288e
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD
Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A .gitkeep file is an unofficial convention used in Git to keep and
track empty directories, as Git does not track empty folders by default.
This could be needed when one mainboard variant has an include directory
but another doesn't. If the directory is added to the include, it could
be easier to just create an empty include directory with a .gitkeep file
in it to keep things from failing.
Change-Id: I34b2ffa4d748d82e26867ecd5b9149301300e6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
4608KB (4.5MB) to incorporate the QTEE FW and its config files.
TEST =Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I69ce0f3cff2cae110a21417245c425ee8bcf1e6c
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rename `common/dsi.c` to `common/dsi_common.c` since this file is used
by all SoCs. Rename `common/mtk_dsi_common.c` to `common/dsi_v1.c`, as
this file serves as the v1 implementation for all SoCs except mt8173.
These changes help clarify file usage and improve code readability.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie711175434febce149a22742d78132842a6ec329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89655
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Now that the PinMux is correctly configured, everything works
as it should without having FSP touch the GPIOs.
Change-Id: Ieec678594f49f3aa003ade29aad85b24ec03f1ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
We use winbond, gigadevice spi flash, and will use spi flash from other vendors in the future, so we have enable all SPI Flash drivers.
BUG=b:442967024
BRANCH=None
TEST=emerge-bluey coreboot chromeos-bootimage
Change-Id: Icb9eeea90e924d412ad782ccf1ac390707f27314
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89641
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design
BUG=b:446813859
TEST=emerge-fatcat coreboot
Change-Id: I193951036abb9a37af6583de0b1401501524b2d8
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
None of these boards strictly "need" an ITE binary, so remove the
Kconfig option. This leaves the logic to add a binary untouched,
so it can be added if desired.
Change-Id: I6cd674a794cac51900b9a11c434b25e28a052b6a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touch controller's I2C bus speed configuration was previously set
directly through register values. This update introduces the use of the
I2C speed enum type to specify the desired connection speed, improving
clarity and reducing the risk of errors. A mapping function has been
added to convert the I2C speed enum into the appropriate register
value, factoring in the SoC's specific divider configuration. This
change ensures that the speed assignment aligns with the expected
operational parameters of the Panther Lake SoC touch controller.
BUG=none
TEST=Boot Fatcat board to OS and verify that the I2C speed assignments
are correct for the register value in SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I32e71ddcab77af2119c012bd3276f83c1bcea954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Adjust fingerprint power sequence to let the time interval between PP3300_MCU and MCU_RST_ODL H(GPP_E7) is 5.1ms(before is 1.1s), meet spec 5.95ms.
BUG=b:411558536
BRANCH=none
TEST=Build and boot to OS. Verify fingerprint power sequence by
EE colleagues.
Change-Id: Ic93af108144a3f227024a8749e0cf88b2f2d90ff
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Move mtk_dsi_reset() from mtk_mipi_dphy.c to mtk_dsi_common.c so that it
can also be used when using the C-PHY interface, improving code reuse.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I3f080127af4411584f66e307f7d2b13abbb051bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89619
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Recent GCC versions (>=12) warn about out-of-bounds accesses when
writing through *(volatile uint8_t *)dest in endian.h.
This is a false positive since these pointers intentionally alias
hardware/physical memory.
Change-Id: Ia47aa1214998dbc17bd4a58f7d996bcc6fff7b6a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The amdfw.rom will be divided into 3 parts:
PSP Level 1, PSP Level 2A, PSP Level 2B.
The two ISHs are close to L1 and can be combined as a CBFS module.
To do that, move the new_psp_dir for L1 and L2 to separated branches.
The final sequence is EFS, PSP L1, ISH A, ISH B, PSP L2A, BIOS L2A,
PSP L2B, BIOS L2B.
TEST=Google/Skyrim
Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Select HAVE_ACPI_TABLES & PCI for QEMU riscv virt machine mainboard. Add
an empty dsdt.asl to fit current build process, but it will not actually
be used since QEMU has its own method of providing DSDT blob.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt,aia=aplic-imsic,acpi=on -bios
build/coreboot.rom -nographic -pflash build/coreboot.rom".
Change-Id: If8c9b5d86adb69afdcb4bf320d6353b2b2acfb31
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89562
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the CS42L43 codec on SoundWire link 3 and the CS35L56
amplifiers on SoundWire link 2.
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
{
Device (SW20)
{
Name (_ADR, 0x00023001FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
Device (SW21)
{
Name (_ADR, 0x00023101FA355601) // _ADR: Address
Name (_DDN, "Right Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
BUG=b:444122406, b:444302600
TES=emerge-lapis coreboot
Change-Id: Ic73d705655bdc0a4a8140feafa28aceb2fc25ad3
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot does not use the nds32le-elf toolchain at all, but it causes
build issues in the CI. So drop it from the default builds. It can
still be built by using buildgcc.
Change-Id: I5e5e5b6914265d6aff14c011062db268db4acf6b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89317
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a null pointer check to ensure that the SoC-specific
function to retrieve I2C bus speed is properly mapped before attempting
to call it. Without this check, systems may crash during boot when the
function pointer is not initialized. The issue occurs when the
touchscreen or touchpad is configured to use THC-I2C via CBI fw_config,
but the underlying SoC doesn't provide the required I2C speed function
implementation.
BUG=none
TEST=Boot Fatcat board to OS with CBI fw_config selecting touchscreen or
touchpad using THC-I2C. Verify no crash occurs during boot and touch
devices function properly.
Change-Id: Ib982f4435aa506f2b9203f81140366addc6559f3
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Originally, there were separate EC firmware builds for the smart
battery (SB) and non-SB versions of the starlite_adl board, but those
have long since been unified. Squash the board variants into a single
board which supports both SB and non-SB boards.
Adjust the board description to reflect that it will support both the
existing N200 and upcoming N355 flavors.
TEST=build/boot starlite_adl on both SB and non-SB boards, verify
battery and all other features function normally.
Change-Id: I2461a094f2455ce333132ffa9f2f83967ae0e927
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a CFR setup menu option to enable/disable the USB micro-SD card
reader, but restrict it to newer boards which use the MXC
accelerometer, as those boards have the card reader on USB2 port 4,
rather than shared with the detachable keyboard on port 3.
TEST=build/boot on starlite_adl boards with and without the MXC
accelerometer, verify only boards with it have the CFR option
to disable the card reader shown, and that the option works
as expected.
Change-Id: I9255d008c6f322d01390ed9f19e4e963cf04eeb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Create the ruby variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:446771934
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_RUBY
2. Run part_id_gen tool without any errors
Change-Id: Ie5f4a152d792f241a0044f18653b5363e1637b49
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89327
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During Uldrenite development, the ISH UART port design and VR settings
were changed, so the switching mechanism was implemented based on the
board ID. Uldrino adopts the latest Uldrenite design; however, its
board ID starts from 0. To resolve this issue, an additional FW_CONFIG
field is added to further distinguish between Uldrenite and Uldrino.
BUG=b:450182476
TEST=Verified the ISH log and used the servod board to dump the CPU
log for checking PMC Descriptor Record 7 at offset 0xC33.
Change-Id: Id24659d6f910de1d3da36c5da808fd768dbdbc37
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89457
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Due to only 1A on DB, the test item of FAFT EC
firmware.DevInsertUSBScreen.insert_usb would be captured much error
message to detect C1 if set the flag.
And then missed to capture the correct message when running the test.
Therefore, removed the DB_1A for pmc_mux on daughter board to fix
the issue.
BUG=b:451436640
TEST=USE="${USE} -project_all project_craaskyu2" emerge-nirva \
coreboot chromeos-zephyr chromeos-bootimage
Confirm firmware.DevInsertUSBScreen.insert_usb PASS.
Change-Id: I6b1a3c99d422c99103818556365b0e5929a18dbf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89538
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Issue=ACP is not active in S3 state and audio playback doesnt work
Fix=Introduce a config option to control this setting.
TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.
Change-Id: Ifbd3e72a4d018e4a14d9459dd3a6804dd27050e4
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89610
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the CS35L56_FAMILY and CS42L43 SoundWire driver configs in
Kconfig to ensure support amp cs35l56 and codec cs42l43 on lapis.
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
{
Device (SW20)
{
Name (_ADR, 0x00023001FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
Device (SW21)
{
Name (_ADR, 0x00023101FA355601) // _ADR: Address
Name (_DDN, "Right Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
BUG=b:444122406
TEST=emerge-fatcat coreboot and dump ssdt.asl
Change-Id: Icab7e38bb5c2733f1bd2a7ddd21b56ace01e64af
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89593
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
CS42L43 contains a range of optional properties which control the
behaviour of jack and accessory detect, and are added here.
These properties are documented in the Linux kernel source code, in the
file:
linux/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml
which contains names, descriptions, valid and default values.
Being optional, these properties will be ignored if not specified.
Change-Id: I53fbed81df9157022384d5879c9d9ed351641ab5
Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously, only the EDP display path was supported due to incorrect
mutex bitfield assignments and incomplete main path setup logic. This
commit corrects the mutex bitfield assignments after reviewing the
datasheet, and updates the main path setup logic to enable support for
both EDP and DSI display paths, improving overall compatibility.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=Check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: Ic3f901b9dff0a7ec9188212d2311b8394cf5c0e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [Window 1: 1.50GB]
[INFO ] * Base: f0000000, Size: e000000, Tag: 200 [Window 2: 224MB]
kernel before:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window] [PM02: 224MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/swanky with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: Ibb61d3188f75a963e9417685c2808b27055b46d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [Window 1: 1.50GB]
[INFO ] * Base: f0000000, Size: e000000, Tag: 200 [Window 2: 224MB]
kernel before:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window] [PM02: 224MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/edgar with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: I86c38b6f0d3e31affb578dc7a1bf5c8109714bf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Broadwell SoC boards (which use Haswell's northbridge ACPI),
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the dynamically-sized PM02 PCI MMIO window above
MMCONF to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 70000000, Tag: 200 [Window 1: 1.75GB]
[INFO ] * Base: f4000000, Size: a000000, Tag: 200 [Window 2: 160MB]
kernel before:
[mem 0x80000000-0xefffffff window] [PM01: 1.75GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xefffffff window] [PM01: 1.75GB]
[mem 0xf4000000-0xfebfffff window] [PM02: 172MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/lulu with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: I83fa8ca7f9edfd7d185895f8bbff15ee9895d1ff
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configure the GPP_E16 reset line for the touch panel as a GPO.
Configure GPP_E17 to a no-connect by default.
BUG=b:452845001
TEST=`emerge-ocelot coreboot chromeos-bootimage`, flash an ocelotite4es
and verify it can boot to kernel without crashing.
Change-Id: I9ba2009252b84fb85356ef65e7b37017f9d2af43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89630
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the power limit and voltage regulator parameters for
the Panther Lake SoC to align with the recommendations from the Power
Map 2.0 document (#813278). The update addresses discrepancies between
the previous configuration and the optimal settings specified in the
Power Map 2.0 document, ensuring better performance and efficiency.
TEST=Power and Performance team verified that Fatcat devices meet
requirements with these settings.
Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Shaik Sameeruddin <shaik.sameeruddin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89318
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Rather than boards configuring a handful, have common code
configure all relevant ones for the SOC.
Change-Id: I06f202378dd26d99a4fb17f6195dd3fb4df61430
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89525
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This avoids storing the same files in 5 different places in the tree.
Change-Id: I84bd5705613947444f48331d1a2d06b1ab71b2f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Allow mainboard vendors to have common code, controlled by a new
Kconfig option MB_COMMON_CODE.
Change-Id: I5b97b26a70fbbe2e3f659f01aa00b16b76167f88
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89531
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
