The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
If it's mismatched, the TBT port will timeout.
TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77567
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On GNR, there are CXL Type-3 memory windows covered under TOHM. The
current 4GB to TOHM DRAM reporting doesn't work on GNR.
Use MemoryMapDataHob to add high RAM resources as a generic
mechanism for GNR and previous generation SoCs.
TEST=Build and boot on intel/archercity CRB
TEST=Build and boot on intel/beechnutcity CRB
(with topic:"Xeon6-Basic-Boot")
Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes the following warning with clang (18.1.6):
src/soc/mediatek/mt8196/gpio_eint.c:259:44: error: '_Static_assert' with no message is a C23 extension [-Werror,-Wc23-extensions]
259 | _Static_assert(ARRAY_SIZE(eint_data) == 293);
| ^
|
Change-Id: I934b6d7ee8e8a0c204a4e328331c3ff3cd0f07de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84618
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for SPI/flash, LPC/eSPI, MCH and
add pci vendor/product description.
References:
* CPU: Linux kernel
* GPU: Linux kernel
* GPU: https://dgpu-docs.intel.com/devices/hardware-table.html
* Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series
Processors for IoT Applications, February 2023, 636722
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Ida852f3c991cdd036d9c282f9cabceb23c765e25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75214
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When parsing XIP stages only compare PT_LOAD phdrs. Currently coreboot
stages only use PT_LOAD phdrs.
Change-Id: I305b25032a3c4a9fdefc76cad77fafdb862a604c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The LTE module RW101R-GL provide a hardware pin to enable/disable
WWAN RF function.The function is disabled in default and is
controlled by the AT command.Therefore,set the WWAN_RF_DISABLE
Pin to NC, and it has been pull-high by hardware desgin.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify the WWAN on/off function in OS.
Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
The method "FUNC" allows 1 argument, so remove the
incorrectly referenced and unused second arguemnt.
This fixes:
ToInteger (Arg1, Local1)
Error 6006 - ^ Method argument is not initialized (Arg1)
Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
QEMU aarch64 boots to payload when compiled with clang.
Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74501
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes building inline assembly that uses SIMD registers. This is
for instance the case in the vboot library.
Change-Id: I24fa9d9f81430ea3ecd40de4304a10c6e235fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Clang builds slightly larger binaries so increase the section.
The qcsdi is used for an external blob that is currently not in use so
reducing the size is fine for now.
Change-Id: Ide01233f209613678c5408f1afab19415c1071be
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X`
Kconfigs, as they are no longer necessary for handling FSP global reset
requests.
Previously, these Kconfigs were used to select a specific 32-bit reset
status code. However, with the introduction of FSP 2.4 and 64-bit
interfaces, the global reset status code can now vary between
architectures.
To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET`
config to a common default value (depending upon most commonly used
global reset status code) based on the interface:
- 0x40000003 for 32-bit FSP interfaces
- 0x4000000000000003 for 64-bit FSP interfaces
This default can be overridden if an FSP implementation uses a
different status code (for example: Apollo Lake selects different FSP
reset status code as 0x40000005).
By removing the SoC-specific configurations, this change simplifies
global reset handling and ensures compatibility across different FSP
versions and platforms.
Below table shows the relationship between Platform, FSP and FSP Global
Reset Status:
+-----------------+--------------+-------------------------+
| Platform | FSP | Global Reset Status |
+-----------------+--------------+-------------------------+
| Alder Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Apollo Lake | 32-bit | 0x40000005 |
+-----------------+--------------+-------------------------+
| Cannon Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Elkhart Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Jasper Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Meteor Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Sky Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Tiger Lake | 32-bit | 0x40000003 |
+-----------------+--------------+-------------------------+
| Panther Lake | 64-bit | 0x4000000000000003 |
+-----------------+--------------+-------------------------+
BUG=b:347669091
TEST=Verified FSP requested global reset functionality on google/rex0
(32-bit) and google/rex64 (64-bit) platforms.
w/ 32-bit FSP:
```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status
40000003
FSPS, status=0x40000003
FSP: handling reset type, status=0x40000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```
w/ 64-bit FSP:
```
(Wdt) AllowKnownReset
[FspResetSystem2] FSP Reset Initiated
FSP returning control to Bootloader with reset required return status 3
FSPS, status=0x4000000000000003
FSP: handling reset type, status=0x4000000000000003
GLOBAL RESET!
global_reset() called!
HECI: Global Reset(Type:1) Command
```
Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The mock/arch/cache.h file exists for libpayload unit tests. However,
the default implementations (as empty macros) in it make these functions
difficult to mock in unit tests.
Therefore, we follow what's done for mock/arch/io.h, by only including
function declarations in the header. Each test is expected to implement
mocks for these cache functions when required.
Change-Id: Ie4383bf95435fd7d74d624b19b79b5a117cf6d00
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
The `handle_range` function in `kconfig_lint` was failing to correctly
handle large hexadecimal values (64-bit value) due to limitations with
Perl's handling of standard integers.
This commit modifies the function to use the `bigint` pragma, enabling
it to handle arbitrarily large integers. This prevents issues with
64-bit hexadecimal values and ensures accurate comparisons for range
validation.
Change-Id: I402bb9bec9ba5bfb79b4185f35228c41d4a7b674
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84575
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `fsp_get_pch_reset_status()` function returns a FSP reset status
code. This change corrects its return type from `uint32_t` to
`efi_return_status_t` to ensure consistency with the FSP API and
prevent potential issues caused by type mismatch.
This correction is necessary for compatibility with both 32-bit and
64-bit FSP interfaces. The change also updates all callers of this
function in the Meteor Lake and Panther Lake SoCs to use the correct
return type.
Includes `fsp/api.h` to provide the `efi_return_status_t` definition.
BUG=b:347669091
TEST=Verified global reset functionality on google/rex0 (32-bit) and
google/rex64 (64-bit) platforms.
Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84571
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Power Resource for Intel Bluetooth, that can reset
the Bluetooth using the delay configured in the DSM.
Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi
driver.
Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84598
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It should be in HEX.
Change-Id: I15a354bae414ad94a2f76030b3099179022b935c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84546
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The platform uses eSPI so these are not needed.
Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SMMSTORE to the default FMAP to allow using UefiPayload on
this board that requires a non-volatile variable store.
TEST: Booted an UEFI compatible OS using EDK2 as payload.
Change-Id: I32fb0a882c62e42da9f3caec54f8d33333fc8598
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84161
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to define ACPI devices for USB-C ports using UCSI. When
defining the typec configuration do not set mux/retimer information.
cros_ec_ucsi does not support setting USB muxes.
BUG=b:349822718
TEST=emerge-brox coreboot chromeos-bootimage. Boot to OS on brox,
confirmed that there are ACPI devices for each USB-C port and
cros_ec_ucsi correctly matched the ACPI devices ("ls -l
/sys/class/typec" with an update to add an ACPI match table to
the cros_ec_ucsi driver).
Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652
Signed-off-by: Jameson Thies <jthies@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84404
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EBDA (Extended BIOS Data Area) is a memory area below 0xA0000 and
one of the default areas where OS will scan ACPI RSDP pointer from.
coreboot's default EBDA's starting address is 0xF6000, which is in
PAM (Programmable Attribute Map) F-segment's scope. For some platforms
without writeable PAM-F segment (e.g. some simics virtual platforms),
corboot's default EBDA is not writable.
Make DEFAULT_EBDA_LOWMEM, DEFAULT_EBDA_SEGMENT, DEFAULT_EBDA_SIZE
as Kconfig items so that coreboot's EBDA could be relocated to a
writable low memory place.
Change-Id: Icd7ba0c902560f7d498934392685dc2af9c5ce09
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch updates the naming scheme used for the GPP bridges.
The naming scheme now matches what we also have on phoenix.
Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It aligns the names in the datasheet with the one in the code. It also
removes and adds some.
Resource: Document 57254 Chapter 15.3.5
TODO it may very well be that I don't have the full truth, because most
of these register just have a different name and some of these names
like ESPI seem more recent that for example LPC.
Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
coreboot doesn't have a leading zero in gpio < 10.
E.g. G00 -> G0
Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84190
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
After reboot, the system does not need to serve pending IRQ from
systimer. Therefore, clear systimer IRQ pending bits in init_timer().
For that to work, the systimer compensation version 2.0 needs to be
enabled.
TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This should be the sane default, as having this option enabled when the
AT24RF08C (Asset Identification EEPROM) is not present on the mainboard
can cause SMBIOS table entries to become "*INVALID*". This can,
for example, result in strange hostnames when an OS installer uses
SMBIOS information to automatically generate one. On the other hand,
the coreboot generated SMBIOS tables will at least always contain basic
information. Therefore, this driver should be treated as an enhancement
rather than a default.
Currently, the following mainboards have this option disabled:
- ThinkCentre M710s
- ThinkCentre M700 / M900 Tiny
- Haswell ThinkPads
- ThinkPad T440p
- ThinkPad W541
Therefore, we can remove this option entirely on these mainboards. Note
that there may be other mainboards which do not have this chip present
but still have the option enabled. However, this requires a more
detailed investigation which would be out of scope of this change.
TESTS=Timeless builds on lenovo mainboards produce the same binary.
config INCLUDE_CONFIG_FILE
default n
Was temporarily added to `mb/lenovo/Kconfig` during these tests, as
while the configuration does not change, the order of entries do.
Therefore, technically producing a different binary when included.
Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This corrects the mismatch found in the verb tables of Monroe Chromebase
and Link Chromebook.
The verb data was not aligned to a multiple of 4, therefore an entry was
repeated as padding.
This was found due to the `_Static_assert()` from CB:84360 failing.
TEST=Tested on LINK under Linux and Win11, audio working properly under both.
Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84414
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The verb data was not aligned to a multiple of 4, therefore an entry was
repeated as padding. This has not been tested.
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows to configure a default screen rotation in 90-degree
steps. The framebuffer contents will then be displayed rotated,
by the same amount in the other direction; i.e. if you turn the
screen to the left, the picture has to be rotated to the right
to accommodate.
This is only supported by libgfxinit from Skylake / Apollo Lake
on (earlier GPUs didn't support the 90-degree steps anyway) and
it only works with the linear-framebuffer option.
Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
IT8613E EC space is divided into 3 banks selectable by EC index 0x06
bits 6:5. Bank0 mostly contains the ITE EC registers known by
coreboot's ITE EC driver. Bank1 contains SB_TSI and PECI temperature
reading registers. Bank2, however, contains additional registers used
to select the temperature source reported in TMPIN reading registers,
PECI bridge registers as well as FAN2-5 controls and extra vectors.
Dump the additional banks using extra-selectors.
Based on non-public IT8613E Preliminary Specification V0.3.
TEST=Perform the IT8613E dump on Hardkernel ODROID H4+.
Change-Id: Ic8fdc56d1b0fbe811e13bc6b800512af654c1cb6
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Poweroff does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/poweroff.
BUG=b:364193909
TEST=emerge-brox coreboot
Change-Id: I0108be4e5e7c0265aae0f16fd4e2b7cbe5936112
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84412
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update DTT settings according to b:348285763#comment20 in
order to increase the limit of the charging current to 3A.
BUG=b:348285763
TEST=emerge-brox coreboot, and thermal engineer verifies OK.
Change-Id: I24978afd819666f635c85f2be9b71d39e0a39f27
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84527
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify start-up timing for WWAN RW101R-GL to follow spec:
PWR_EN H H H
FCPO# Tpr H H
RESET# L Ton H
Tpr: delay for Power stable (>0ms)
Ton: delay for reset time (>20ms)
BUG=b:349698817
BRANCH=None
TEST= Build firmware and verify on jubilant with RW101R-GL
Measure the start-up timing sequence to meet spec
Boot up in OS, and confirm WWAN can connect to cell site
Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
If make is ran a second time after an initial clean compile, the entire
rom will be rebuilt. Subsequent calls to make will not rebuild the rom.
This initial rebuild was due to build/util/kconfig/conf being newer than
config.h, and the subsequent rebuild of the header marked everything
else as out of date. The reason conf was newer than config.h is because
it was being treated as an intermediate file [1]. In the rule for
config.h, conf is a prerequisite, but since it is treated as an
intermediate, its rule will not be run if config.h exists and all the
prerequisites of conf (i.e. its source files) are also up to date.
On a clean build after a make menuconfig, config.h exists, satisfying
these conditions. In this case, config.h is treated as being up to date
even though conf does not exist. However, if another target does not
exist and also has conf as a prerequisite, conf will then be built so
that the target can be built. This caused conf to be newer than
config.h, but by default GNU Make deletes intermediate files after a
build which would prevent conf from affecting config.h on subsequent
rebuilds.
However, commit dd6efce934 ("Makefile: Add .SECONDARY") adds the
.SECONDARY special target, which prevents intermediate files from being
deleted after the build [2]. Thus, conf persists to the first no-op
build, making config.h out of date. Since config.h is updated during
this first rebuild, conf is no longer newer than it, and thus subsequent
no-op builds behave as expected.
Fix this by preventing conf from being treated as an intermediate file
by adding it as a prerequisite of the .NOTINTERMEDIATE special target,
which causes conf to always be rebuilt if it does not exist. Thus, on
the initial clean compile, config.h will be updated after building conf
as a prerequisite, preventing config.h from being marked out of date on
a subsequent rebuild.
[1] https://www.gnu.org/software/make/manual/html_node/Chained-Rules.html
[2] https://www.gnu.org/software/make/manual/html_node/Special-Targets.html
Change-Id: I98c49d47f811e5cceebce7b7d54b282c773734e3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Many sources include device.h and thus static.h, but many only need the
function declarations and type definitions, not the compiled devicetree
from sconfig. This causes many unnecessary recompiles whenever the
devicetree is updated due to the dependency. Address this by moving the
config_of_soc macro directly into the generated static.h header, as it
seems to be the only line in device.h that actually requires static.h.
For now, static.h remains included in device.h so that the build is not
affected. Subsequent commits will include static.h directly into sources
that actually need it, after which it can be dropped from device.h.
Some statistics for C objects:
Dell Latitude E6400 (GM45/ICH9):
669 total objects
181 depend on static.h
2 require static.h
Dell Latitude E6430 (Ivy Bridge/Panther Point):
693 total objects
199 depend on static.h
3 require static.h
Lenovo ThinkCentre M700 / M900 Tiny (Kaby Lake):
794 total objects
298 depend on static.h
23 objects require static.h
MSI PRO Z690-A (WIFI) DDR4 (Alder Lake):
959 total objects
319 depend on static.h
25 require static.h
The number of objects was determined by grepping the build log for
calls to CC, the number of objects that depend on static.h was
determined by grepping for calls to CC after touching static.h, and the
number of objects that actually require the static.h related lines from
device.h was determined by grepping for objects that failed to build
after removing the static.h lines from device.h and running make with
the --keep-going flag.
Change-Id: I7c40135bf2815093b81e47201c38b7d0a6ac8fa8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
FSP-M UPDs are programmed according to the configuration (Kconfig and
device tree).
BUG=348678529
TEST=Memory is initialized successfully and hardware is programmed as
desired on Intel pantherlake reference board.
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
