vc/intel/fsp: Update PTL FSP headers from dummy headers to v2382_01
Update generated FSP headers for Panther Lake from v2382_01 Changes include: - Update FspmUpd.h, FspsUpd.h, MemInfoHob.h and FirmwareVersionInfo.h BUG=b:348678529 TEST=Able to build google/fatcat Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2020 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ronak Kanabar
Subrata Banik
parent
76a16f8e8a
commit
7e5765710a
4 changed files with 5366 additions and 31 deletions
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@ -1,16 +1,8 @@
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/** @file
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Header file for Firmware Version Information
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Intel Firmware Version Info (FVI) related definitions.
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@copyright
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Copyright (c) 2015 - 2024, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License which accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
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@ -22,6 +22,35 @@
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#pragma pack (push, 1)
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extern EFI_GUID gSiMemoryS3DataGuid;
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extern EFI_GUID gSiMemoryS3Data2Guid;
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extern EFI_GUID gSiMemoryInfoDataGuid;
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extern EFI_GUID gSiMemoryPlatformDataGuid;
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#define MAX_NODE 2
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#define MAX_CH 4
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#define MAX_DDR5_CH 2
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#define MAX_DIMM 2
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#define MAX_RANK_IN_CHANNEL (4)
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#define MAX_SDRAM_IN_DIMM (5)
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// Must match definitions in
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// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
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#define HOB_MAX_SAGV_POINTS 4
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///
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/// Host reset states from MRC.
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///
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#define WARM_BOOT 2
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#define R_MC_CHNL_RANK_PRESENT 0x7C
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#define B_RANK0_PRS BIT0
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#define B_RANK1_PRS BIT1
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#define B_RANK2_PRS BIT4
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#define B_RANK3_PRS BIT5
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// @todo remove and use the MdePkg\Include\Pi\PiHob.h
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#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
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#ifndef __HOB__H__
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typedef struct _EFI_HOB_GENERIC_HEADER {
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@ -40,6 +69,17 @@ typedef struct _EFI_HOB_GUID_TYPE {
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#endif
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#endif
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///
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/// Defines taken from MRC to avoid having to include MrcInterface.h
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///
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//
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// Matches MAX_SPD_SAVE define in MRC
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//
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#ifndef MAX_SPD_SAVE
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#define MAX_SPD_SAVE 29
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#endif
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//
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// MRC version description.
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//
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@ -97,16 +137,231 @@ typedef enum {
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} MRC_BOOT_MODE;
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#endif //__MRC_BOOT_MODE__
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//
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// Matches MrcDdrType enum in MRC
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//
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#ifndef MRC_DDR_TYPE_LPDDR5
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#define MRC_DDR_TYPE_LPDDR5 0
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#endif
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#ifndef MRC_DDR_TYPE_DDR5
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#define MRC_DDR_TYPE_DDR5 1
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#endif
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#ifndef MRC_DDR_TYPE_UNKNOWN
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#define MRC_DDR_TYPE_UNKNOWN 2
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#endif
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#define MAX_PROFILE_NUM 7 // number of memory profiles supported
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#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
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#ifndef MAX_RCOMP_TARGETS
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#define MAX_RCOMP_TARGETS 5
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#endif
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#ifndef MAX_ODT_ENTRIES
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#define MAX_ODT_ENTRIES 11
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#endif
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#ifndef MAX_COPY_DIMM_DFE_TAPS
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#define MAX_COPY_DIMM_DFE_TAPS 2
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#endif
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#define MAX_TRACE_REGION 5
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#define MAX_TRACE_CACHE_TYPE 2
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//
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// DIMM timings
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//
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typedef struct {
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UINT32 tCK; ///< Memory cycle time, in femtoseconds.
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UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
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UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
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UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
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UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
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UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
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UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
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UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
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UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
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UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
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UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
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UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
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UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
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UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
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UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
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UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
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UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
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UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
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UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
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UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
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UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
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UINT8 Resv[2]; ///< Reserved.
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} MRC_CH_TIMING;
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typedef struct {
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UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
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} MRC_IP_TIMING;
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///
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/// Memory SMBIOS & OC Memory Data Hob
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///
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typedef struct {
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UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
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UINT8 DimmId;
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UINT32 DimmCapacity; ///< DIMM size in MBytes.
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UINT16 MfgId; ///< Dram module manufacturer ID
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UINT16 CkdMfgID; ///< Clock Driver (CKD) Manufacturer ID
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UINT8 CkdDeviceRev; ///< Clock Driver (CKD) device revision
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UINT16 DramMfgID; ///< Manufacturer ID code for DRAM chip on the module
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UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
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UINT8 RankInDimm; ///< The number of ranks in this DIMM.
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UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
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UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
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UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
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UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
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UINT16 Speed; ///< The maximum capable speed of the device, in MHz
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UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
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UINT8 Banks; ///< Number of banks the DIMM contains.
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UINT8 BankGroups; ///< Number of bank groups the DIMM contains.
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UINT8 DeviceDensity; ///< Device Density in Gb
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} DIMM_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this channel should be used.
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UINT8 ChannelId;
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UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
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MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
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DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
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} CHANNEL_INFO;
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typedef struct {
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UINT8 Status; ///< Indicates whether this controller should be used.
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UINT16 DeviceId; ///< The PCI device id of this memory controller.
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UINT8 RevisionId; ///< The PCI revision id of this memory controller.
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UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
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CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
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} CONTROLLER_INFO;
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//
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// Each DIMM Slot Mechanical present bit map
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//
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typedef struct {
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UINT8 MrcSlotMap[MAX_NODE][MAX_CH];
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} MRC_SLOTMAP;
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typedef struct {
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UINT64 BaseAddress; ///< Trace Base Address
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UINT64 TotalSize; ///< Total Trace Region of Same Cache type
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UINT8 CacheType; ///< Trace Cache Type
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UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
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UINT8 Rsvd[2];
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} PSMI_MEM_INFO;
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/// This data structure contains per-SaGv timing values that are considered output by the MRC.
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typedef struct {
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UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
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MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
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MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
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UINT16 MaxMemoryBandwidth; ///< Maximum theoretical bandwidth in GB/s supported by GV
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} HOB_SAGV_TIMING_OUT;
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/// This data structure contains SAGV config values that are considered output by the MRC.
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typedef struct {
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UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
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UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
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HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
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} HOB_SAGV_INFO;
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typedef struct _PPR_RESULT_COLUMNS_HOB {
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UINT8 PprRowRepairsSuccessful;
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UINT8 Controller;
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UINT8 Channel;
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UINT8 Rank;
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UINT8 BankGroup;
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UINT8 Bank;
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UINT32 Row;
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UINT8 Device;
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} PPR_RESULT_COLUMNS_HOB;
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/**
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Memory Info Data Hob
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<b>Revision 1:</b>
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- Initial version. (from MTL)
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<b>Revision 2:</b>
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- Added MopPackages, MopDensity, MopRanks, MopVendor fields
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**/
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typedef struct {
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UINT8 Revision;
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UINT16 DataWidth; ///< Data width, in bits, of this memory device
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/** As defined in SMBIOS 3.0 spec
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Section 7.18.2 and Table 75
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**/
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UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
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UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
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UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
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/** As defined in SMBIOS 3.0 spec
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Section 7.17.3 and Table 72
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**/
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UINT8 ErrorCorrectionType;
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SiMrcVersion Version;
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BOOLEAN EccSupport;
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UINT8 MemoryProfile;
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UINT32 TotalPhysicalMemorySize;
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UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
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UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
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UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
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BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
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UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
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UINT8 RefClk;
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UINT32 VddVoltage[MAX_PROFILE_NUM];
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UINT32 VddqVoltage[MAX_PROFILE_NUM];
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UINT32 VppVoltage[MAX_PROFILE_NUM];
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UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
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UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
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INT8 DimmDFE[MAX_PROFILE_NUM][MAX_DDR5_CH][MAX_DIMM][MAX_COPY_DIMM_DFE_TAPS];
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CONTROLLER_INFO Controller[MAX_NODE];
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UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
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HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
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BOOLEAN IsIbeccEnabled;
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UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
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UINT8 MopPackages; ///< Mop DRAM package population
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UINT8 MopDensity; ///< Mop DRAM die density
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UINT8 MopRanks; ///< Mop Number of ranks
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UINT8 MopVendor; ///< Mop DRAM vendor ID
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UINT8 PprRanInLastBoot; ///< Whether PPR ran in the prior boot
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UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows
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UINT16 PprRepairFails; ///< PPR: Counts of repair failure
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UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
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UINT16 PprRepairsSuccessful; ///< PPR: Counts of repair successes
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PPR_RESULT_COLUMNS_HOB PprErrorInfo; ///< PPR: Error location
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UINT8 PprAvailableResources[MAX_NODE][MAX_CH][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device
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} MEMORY_INFO_DATA_HOB;
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/**
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Memory Platform Data Hob
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<b>Revision 1:</b>
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- Initial version.
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<b>Revision 2:</b>
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- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
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**/
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typedef struct {
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UINT8 Revision;
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UINT8 Reserved[3];
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UINT32 BootMode;
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UINT32 TsegSize;
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UINT32 TsegBase;
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UINT32 PrmrrSize;
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UINT64 PrmrrBase;
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UINT32 GttBase;
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UINT32 MmioSize;
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UINT32 PciEBaseAddress;
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PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
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PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
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BOOLEAN MrcBasicMemoryTestPass;
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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