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soc/amd/glinda: Update gpp bridge naming scheme

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This patch updates the naming scheme used for the GPP bridges.
The naming scheme now matches what we also have on phoenix.

Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Maximilian Brune 2024-08-09 12:49:29 +02:00 • committed by Martin L Roth
commit aed7a871b2
3 changed files with 15 additions and 12 deletions
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7
src/mainboard/amd/birman/devicetree_glinda.cb
View file

@ -158,9 +158,10 @@ chip soc/amd/glinda
device domain 0 on
device ref iommu on end
device ref gpp_bridge_0 on end # GBE
device ref gpp_bridge_1 on end # WIFI
device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_2_1 on end # GBE
device ref gpp_bridge_2_2 on end # WIFI
device ref gpp_bridge_2_3 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)

6
src/mainboard/amd/birman_plus/devicetree_glinda.cb
View file

@ -158,9 +158,9 @@ chip soc/amd/glinda
device domain 0 on
device ref iommu on end
device ref gpp_bridge_0 on end # GBE
device ref gpp_bridge_1 on end # WIFI
device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_2_1 on end # GBE
device ref gpp_bridge_2_2 on end # WIFI
device ref gpp_bridge_2_3 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)

14
src/soc/amd/glinda/chipset.cb
View file

@ -14,13 +14,15 @@ chip soc/amd/glinda
device pci 01.2 alias usb4_pcie_bridge_1 off end
device pci 01.3 alias usb4_pcie_bridge_2 off end
# The PCIe GPP aliases in this SoC match the device and function numbers
device pci 02.0 on end # Dummy device function, do not disable
device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end
device pci 03.0 on end # Dummy device function, do not disable
device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end
device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end