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soc/amd/glinda: Update SCI mapping

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source: PPR #57254 Rev 1.71

Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84381
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maximilian Brune 2024-08-09 14:47:19 +02:00 • committed by Felix Held
commit db96c9634e
2 changed files with 27 additions and 14 deletions
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19
src/soc/amd/glinda/include/soc/pci_devs.h
View file

@ -65,10 +65,6 @@
#define GFX_HDA_FUNC 1
#define GFX_HDA_DEVFN PCI_DEVFN(GFX_HDA_DEV, GFX_HDA_FUNC)
#define XHCI0_DEV 0x0
#define XHCI0_FUNC 3
#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)
#define XHCI1_DEV 0x0
#define XHCI1_FUNC 4
#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC)
@ -89,9 +85,18 @@
#define PCIE_ABC_C_DEVFN PCI_DEVFN(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
#define SOC_PCIE_GPP_C_DEV _SOC_DEV(PCIE_ABC_BRIDGE_DEV, PCIE_ABC_C_FUNC)
#define XHCI2_DEV 0x0
#define XHCI2_FUNC 0
#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
#define XHCI0_DEV 0x0
#define XHCI0_FUNC 0
#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)
#define USB4_XHCI0_DEV 0x0
#define USB4_XHCI0_FUNC 3
#define USB4_XHCI0_DEVFN PCI_DEVFN(USB4_XHCI0_DEV, USB4_XHCI0_FUNC)
#define USB4_XHCI1_DEV 0x0
#define USB4_XHCI1_FUNC 4
#define USB4_XHCI1_DEVFN PCI_DEVFN(USB4_XHCI1_DEV, USB4_XHCI1_FUNC)
/* SMBUS */
#define SMBUS_DEV 0x14

22
src/soc/amd/glinda/xhci.c
View file

@ -25,7 +25,13 @@ static const struct sci_source xhci_sci_sources[] = {
.level = SMI_SCI_EDG
},
{
.scimap = SMITYPE_XHC2_PME,
.scimap = SMITYPE_XHC3_PME,
.gpe = GEVENT_31,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
},
{
.scimap = SMITYPE_XHC4_PME,
.gpe = GEVENT_31,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
@ -41,18 +47,20 @@ enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
return CB_ERR_ARG;
if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
if (dev->path.pci.devfn == XHCI0_DEVFN) {
*gpe = xhci_sci_sources[0].gpe;
return CB_SUCCESS;
} else if (dev->path.pci.devfn == XHCI1_DEVFN) {
if (dev->path.pci.devfn == XHCI1_DEVFN) {
*gpe = xhci_sci_sources[1].gpe;
return CB_SUCCESS;
}
} else if (dev->upstream->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
if (dev->path.pci.devfn == XHCI2_DEVFN
&& dev->device == PCI_DID_AMD_FAM17H_MODELA0H_XHCI2) {
if (dev->path.pci.devfn == XHCI0_DEVFN) {
*gpe = xhci_sci_sources[0].gpe;
return CB_SUCCESS;
} else if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) {
*gpe = xhci_sci_sources[2].gpe;
return CB_SUCCESS;
} else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) {
*gpe = xhci_sci_sources[3].gpe;
return CB_SUCCESS;
}
}