The CPUCP (CPU Control Processor) firmware for X1P42100 is being
loaded as a payload. Compressing this file in CBFS can lead to
loading delays with the early-stage.
Set the compression type to 'none' to ensure the ELF is stored
uncompressed.
BUG=b:449871690
TEST=Able to optimize boot time (tested on google/quartz) by ~200ms.
w/o this patch:
```
fallback/cpucp 0xc7500 simple elf 149498 none
```
w/ this patch:
```
fallback/cpucp 0xc7500 simple elf 496196 none
```
Change-Id: I77418ac05ad950943a538ad1c2976d5cdfe41324
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set defaults for VGA_BIOS_FILE and VGA_BIOS_ID.
TEST=Pre OS graphics init works on AMD/jaguar.
Change-Id: I3bf0e81b0de87abe4a03be8e10274936cf29e628
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The function tlcl2_get_capability() is only linked when Kconfig TPM2
is being selected. Add a guard to not include the SMBIOS code when
TPM2 isn't selected.
TEST=Can compile the fTPM driver when TPM2 isn't selected.
Change-Id: I9385f15fc71c021f9be2bfb874898f76fa71fee4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91775
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files use unit16_t and more, so this should be included.
Change-Id: If08dd6c3267b39cd72fcfaa9803c72260165337d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91815
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
drivers/intel/gma/opregion already provides a weak
mainboard_vbt_filename() implementation that returns "vbt.bin".
Drop the Starlabs overrides that return the same filename and keep only
the remaining board-specific override that still selects an alternate
VBT. This also removes the now-dead overrides left behind after
display-native-resolution VBT selection was dropped.
Change-Id: I89ec4f55d4c4ed3265a8d429c3d399977ad466d7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Allow the build system to specify the variable store position in flash
and update BIOS entry 0x6d when set.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I3888810570897ea509a49fd4bc38d875d7d8be0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
When using ROM Armor, the AMD_BIOS_APOB_NV BIOS directory table
entry needs to be marked as writable. Add support for marking
BIOS directory table entries as writable and set all BIOS directory
files to RO, except for AMD_BIOS_APOB_NV (type 0x63), which is
written at end of coreboot based on the FMAP.
TEST=ROM Armor 3 enabled system can write APOB through PSP mailbox
interface. When the writable bit is not set cannot write APOB
through mailbox interface.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Idce7f4afbdd2246a5c0fc96d27c3c721e4a5b03a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91700
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When ROM Armor is enabled and PSP is not in "capsule update mode",
the PSP can only write to PSP directory entries that have the writable
bit set. As the fTPM PSP trustlet must write to NVRAM regions as part
of the fTPM operation, set the writable bit on such regions.
Fixes crash on PSP side when using ROM Armor and fTPM.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I5668976d687e5f9aa3fc62e91adf6bde5cadb5b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This removes the 'upcoming release' text and updates the statistics
for the 26.03 release tag.
Change-Id: Iecc233664d55b6b3b10a775a2990ec673b371754
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91782
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To comply with the Focal touchscreen module specification and prevent
interference during the power on init and self-calibration process,
the power-on sequence is implemented across different boot stages:
1. GPIO Initialization (Romstage/Ramstage):
- Pull Touch Enable (GPP_F08) High in the early GPIO table (Romstage)
to stabilize Vcc early.
- Pull Touch Report Switch (GPP_E05) High while initializing Touch
Reset (TCHSCR_RST_L, GPP_F16) to Low in the main GPIO table
(Ramstage) to maintain the reset state.
2. Chip Config Stage (Reset De-assertion):
- Implement fw_config_post_gpio_configure() to pull TCHSCR_RST_L High
during the BS_DEV_INIT_CHIPS stage.
- This ensures the reset is released only after Backlight (BL_ON) is
enabled, satisfying the module's calibration requirements.
3. ACPI & Power Management:
- Retain 'stop_gpio' (GPP_E05) in overridetree.cb for S0ix power
saving while removing 'reset_gpio' and 'enable_gpio' to avoid
driver conflicts with the manual boot sequence.
BUG=b:493322404
TEST=Build and boot on moonstone, verify touchscreen power-on
sequence with oscilloscope to match BOE requirements.
Verified on moonstone: Touchscreen is correctly detected and
functional after boot and S0ix resume.
Change-Id: I0fd323e56cd86ae85a40a489513e158b05be2233
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The current implementation executes the mainboard_pre_dev_init_chips
hook at the entry of BS_DEV_INIT_CHIPS boot state. Move this to
the exit to add more delay in execution, change the function name
accordingly.
BUG=b:493322404
TEST=Able to build and boot fatcat
Change-Id: Icec47552f3331457c05cd255ecc1385ec70d6b94
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91777
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update `get_battery_icurr_ma` to use the newly introduced
`spmi_read8_safe` helper. This ensures that transient SPMI arbiter
errors (0xfffffff7) are handled via retries rather than being
immediately treated as zero current.
By validating both the primary (SMB1) and secondary (SMB2) charger
registers with retries, the system avoids entering the power-off
path caused by spurious 0mA readings during early boot or rail
stabilization.
Additionally, using 5ms delay before charger SMB1/2 register read.
BUG=b:436391478
BRANCH=none
TEST=On Bluey, verify that battery current is reported correctly
even if the initial SPMI read encounters a transient failure.
Change-Id: I8dee77ba83798e8e50f8884604c588fe4fda0e0a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91767
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce `spmi_read8_safe` to handle transient SPMI bus errors that
can occur during early power sequencing. This helper implements a
retry mechanism (up to 6 attempts) with a 50ms delay between reads.
Providing a "safe" read wrapper prevents the system from misinterpreting
transient arbiter errors (ERROR_SPMI_READ_FAILED) as valid zero data,
which is critical for preventing premature power-offs when reading
input current .
BUG=b:436391478
BRANCH=none
TEST=Verified that SPMI read failures in the charging applet now
trigger the retry loop and successfully recover on Bluey.
Change-Id: Id1b770d2cd91ccb069933bd9b023b867a7507009
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the logic to detect, set, and handle RTC wake-up events on
the Bluey mainboard.
Key changes:
- romstage: Use the new google_chromeec_is_rtc_event() API to set
the boot mode to LB_BOOT_MODE_RTC_WAKE when an RTC alarm triggers
the boot.
- mainboard: Update is_low_power_boot_with_charger() to include
RTC_WAKE, ensuring the system follows the low-power initialization
path (e.g., entering the charging applet).
- mainboard: Update display_startup() to skip display initialization
during an RTC wake event to conserve power and maintain a "dark"
wake-up state where appropriate.
BUG=b:493760057
BRANCH=none
TEST=Set an RTC alarm via the EC, verify the system boots into the
charging applet path and skips display initialization on Bluey.
Change-Id: Iaa9d1acffa0da014775e3397b877178c9c820ad5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91765
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define CB_BOOT_MODE_RTC_WAKE and LB_BOOT_MODE_RTC_WAKE in the
coreboot table headers. This allows the firmware to communicate
to the payload (such as depthcharge) that the device started
up due to a Real-Time Clock alarm.
Synchronize the change across:
- payloads/libpayload/include/coreboot_tables.h
- src/commonlib/include/commonlib/coreboot_tables.h
BUG=b:493760057
BRANCH=none
TEST=Build coreboot and libpayload. Verify that the new boot mode
is accessible in the payload.
Change-Id: I8f5e118e6965f29498ab5bb46e153bc6d24bc116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91764
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add `google_chromeec_is_rtc_event()` to allow the AP to check if the
EC has posted an `EC_HOST_EVENT_RTC`. This is useful for identifying
wake-up or boot reasons triggered by the real-time clock.
BUG=b:493760057
BRANCH=none
TEST=Build and boot on a board using ChromeEC; verify the API
correctly detects RTC events.
Change-Id: Id62cb6942a5881932eec420c78389e9d78b1e7a9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91763
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Split the Qualcomm QUPV3 SE and GPI firmware loading into two helper
functions: load_qc_se_firmware_early() and load_qc_se_firmware_late().
- Early stage: Loads firmware for the ADSP I2C (Charger/Fuel gauge)
and GPI instances. This is now called via mainboard_init.
Off-mode charging is now part of the early stage operation.
- Late stage: Loads firmware for UART, USB-A retimers, and
Fingerprint SPI. This is now called via mainboard_enable.
This restructure utilizes the chip_operations .init callback to ensure
critical charging-related operation is loaded before subsequent
initialization steps.
Change-Id: I54d41e76b162f80a80117bfe54943dc43b360dae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT for the Bluey board to allow
non-blocking PCIe link training.
Call qcom_setup_pcie_host() during platform_romstage_postram() when
performing a normal boot.
This takes advantage of the asynchronous PCIe initialization logic,
starting the link training early to save approximately 100ms of
blocking wait time in ramstage.
BUG=b:449871690
TEST=Able to save 100ms of the boot time (google/quenbih).
w/o patch:
```
5000:<unknown> 1,224,619 (662)
5001:<unknown> 1,324,851 (100,232)
```
w/ patch:
```
5000:<unknown> 1,098,810 (808)
5001:<unknown> 1,098,928 (118)
```
Change-Id: If758c2fb8f7a6a5bb8c5fe6c1d7b44e988858179
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To support this early hardware initiation, add pcie_common.c and
soc-specific pcie.c to the romstage build when
SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT and PCI Kconfigs are enabled.
This allows the SoC to kick off link training in romstage
and verify the link status later in ramstage.
BUG=b:449871690
TEST=Able to build and boot google/quenbih.
Change-Id: I6f81b88b36f51b55cb47846f9e81d0be8f987825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT to allow the PCIe
link training to proceed without blocking the boot flow.
Refactor qcom_setup_pcie_host into two logical phases:
1. Initiate: Power on endpoints and trigger LTSSM (Romstage).
2. Verify: Wait for link-up status (Ramstage).
When the async Kconfig is enabled, the initiation happens in
romstage, but the blocking 'wait_link_up' call is deferred to
ramstage. This allows other SoC and mainboard initializations to
run in between the hardware link training, reducing overall boot time.
BUG=b:449871690
TEST=Verified PCIe link still enumerates correctly on Bluey with
asynchronous init enabled.
Change-Id: Idf368731325b5efcf4db0d1912a8c75417ef11ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91723
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expand CBFS_MCACHE from 16K to 22K to provide more space for
metadata caching. To accommodate this, shift FMAP_CACHE from
0x14860400 to 0x14861800.
Updated the memory map diagram in memlayout.ld to reflect the
new base address for the FMAP_CACHE region.
TEST=No CBFS related error seen while booting google/quartz.
w/o patch:
```
[ERROR] CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
```
Change-Id: Ic3268c72a4755bd15c6811688eb330c7d753c5ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91698
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When transitioning between boot stages, it is often necessary to move
the Translation Table Base (TTB) from a temporary pre-RAM location
to a permanent post-RAM region.
ARM64 page tables contain absolute physical addresses for lower-level
tables. When moving the TTB from one base address to another, these
internal pointers must be adjusted.
Implement mmu_relocate_ttb() to handle this transition. The logic
copies the tables from _preram_ttb to _postram_ttb and performs a
fixup on all descriptors to reflect the new offset. This ensures
memory mapping remains consistent after the TTB base changes.
BUG=b:436391478
TEST=Verify successful TTB relocation and stable MMU state on Quartz.
Change-Id: I7fdd69bfa82fc3dae919693f4d5d0314687cbef9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Realtek advised leaving the StarFighter speaker path idle with GPIO2
low and LINE2 EAPD disabled when no audio is playing.
Add a "Legacy Speaker Control" CFR option for the Meteor Lake variant
so coreboot can optionally boot the codec in that muted state. This
avoids the cold-boot / G3 speaker pop when paired with the Linux
runtime sequencing fix that asserts EAPD and GPIO2 only for playback.
Keep the option enabled by default so existing kernels continue to use
the legacy speaker setup. Without the matching Linux change, forcing
GPIO2 low at boot would leave the external speaker amp disabled and
result in no speaker output.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I62427d3f13b8a68a58bca4ed7896482da4abf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91662
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drain pending SPI sync SMIs before dropping write protect for SMMSTORE and once more after the command runs. This keeps a stale sync status from leaking into the next request.
Change-Id: I7ba21719a6dafa926b0d5986a253da9cff52575a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In the "AC only" scenario, since the adapter is 65W,
the values of PL2 and PL4 need to be reduced to prevent
the machine from shutting down.
BUG=b:487170924
TEST=emerge-fatcat coreboot, test pass by power engineer
Change-Id: Id0b1f886205f26a5171f21ae43a9360791e0979b
Signed-off-by: WeiHuaLin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91646
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on Autoport with subsequent manual tweaking. The system boots
with an Intel i7-4770K using Haswell NRI. Thanks to Angel Pons for
fixing S3 suspend/resume.
Working:
- Haswell CPUs
- Haswell NRI
- Both DDR3 DIMM slots
- HDMI Port
- DP Port
- All rear USB ports
- Audio Jack
- Ethernet port
- WiFi and M.2
- All SATA ports
- Discrete Graphics (tested with AMD R9 Nano)
- TPM 2.0
- S3 suspend and resume
Not working:
- Rear double-digit display does not show CPU temp.
- Known issue: Broadwell (non-ULT) CPUs are not yet supported in coreboot
Not (yet) tested:
- USB headers
Change-Id: I6813adce267af6bd449f72b0595dfec9277961bf
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91672
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The docs talk about left-shifting SPD addresses by 1. This was necessary
back when mainboard code would directly set the values of the members in
`struct pei_data`, which stopped being the case with commit 1e2821882f
("nb/intel/haswell: Use unshifted SPD addresses in mainboards").
Given that `util/autoport` (which now supports Haswell / Lynx Point) has
documentation on how to figure out the SPD address mapping in a platform
agnostic format, drop the outdated section from Haswell-specific docs.
Change-Id: I3d118b2e116cf2cd0096c8ef27e2fd22e6e548ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Integrate thermal monitoring into the low-battery and off-mode charging
flow.
During battery charging in the ramstage, the system now scans all
thermal zones. If any sensor trips its defined threshold, the system
executes an emergency power-off to protect the hardware from thermal
damage.
TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.
TEST=Verify system shutdown on a thermal trip on Google/Quartz.
Change-Id: Id45d5f097dfb0c7b01e0541e116f5356f59f8269
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91611
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide the SoC-specific hardware definitions for the x1p42100 TSENS
subsystem. This includes the register base addresses for the four
TSENS controllers and the complete mapping of sensor IDs to thermal
zones (including AOSS, CPU, GPU, and NSP).
Each zone is assigned a specific thermal threshold to allow for
emergency shutdown triggers.
TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.
Change-Id: Iffdd0589a3c5318b9754101d7cea40462435de5b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91610
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a generic driver for the Qualcomm Temperature Sensor (TSENS)
V2 hardware block. This driver provides the infrastructure to read
temperature data from hardware status registers and monitor them
against software-defined thresholds.
The driver sign-extends the 12-bit raw temperature values and scales
the output to millidegrees Celsius for accurate monitoring.
TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.
Change-Id: I826df3f86edc30ac57d84f672b487a8b9b51728a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91609
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the required definition for the 806 MHz CPU clock (L_VAL_806MHz).
Update pll_init_and_set by removing the static qualifier so it can be
invoked from the mainboard code.
Test: Built image.serial.bin and verified successful boot on X1P42100.
Change-Id: I8871f6cd64cb386c1042ce42feec4c623e9804e9
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the release notes template for the upcoming June 2026
release of coreboot.
Change-Id: I4a436ba1b649ce1091c6e496768ef7dc41776668
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91730
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.
Change-Id: Id24c2d43c53db7976c98f5936d9d8866a7392ad2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91731
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Produced by running: util/vboot_list/vboot_list.sh
Change-Id: I2c59e921e1160c4df739ad827161ee0af40fec39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91729
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add the OPAL packet builder and unlock logic used by the SMM resume
path. Uses the TCG storage encoder and NVMe Security Send/Receive
helpers to perform the Admin1/User1 Set Global Range unlock sequence.
TEST=tested with rest of patch train
Change-Id: I4cdb16e13c1aeb89648db49672b77598a8b42fac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Faegan is an alias for Krackan2e. This only changes the SoC name in
amdfwtool; the Faegan SoC variant name in the glinda folder will be
renamed later once all remaining patches have been upstreamed, to not
make the upstreaming more difficult than necessary.
Change-Id: I051e163170d4363594dcff4b505d01cabfb3a190
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Glinda is an alias for Strix. This only changes the SoC name in
amdfwtool; SoC folder will be renamed later once all remaining patches
have been upstreamed, since renaming the SoC folder right now, would
just make the upstreaming more difficult.
Change-Id: I10cb9c4a97dd2689fe02329262772b05d24a5896
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Drop send_psp_command_smm() and let the generic send_psp_command()
method handle SMM as special case. This allows to use the same
method in regular code and SMM.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I5dad79e80b97e9d4dfbcd0d84d49eb23ea3f83cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91702
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The colour components are in RGB order in the structure returned by the
ACPI `_PLD` method, so use the same order in the C struct as well. This
has no impact since nobody currently specifies port colours with this.
Change-Id: I11b486faaf73f5da37b973180f23e8b3f19f3f5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91389
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for selecting NVMe or eMMC storage via CFR option on
taeko and taniks variants. Override fw_config_probe() to check the
CFR "storage_device" option and enable/disable the appropriate PCIe
root port based on user selection.
This allows runtime configuration of storage devices while ensuring
only the selected device is initialized, since initializing both
causes neither to be detected.
TEST=build/boot taeko, verify both eMMC and NVMe M.2 storage modules
functional when correct type selected from setup menu.
Change-Id: Ic555f93763736adb5837534b8011aa9c123fea08
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add fw_config_probe_mainboard_override() hook that allows mainboards
to selectively override specific fw_config probes. The hook returns
whether the function handed the probe or not. If set to true, the
hook's 'result' parameter is returned; otherwise, standard fw_config
logic is used automatically.
This enables mainboards to override probes based on runtime conditions
(e.g., CFR options) without reimplementing standard fw_config logic.
The change is backward compatible as the default hook doesn't handle
any probes.
TEST=tested with subsequent patch
Change-Id: I6b9207eb9097ef5296fb5c41d8d1acbfde68b445
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
