arch/arm64: Add debug API to dump MMU page table configuration
To validate complex memory layouts and verify the success of TTB relocations, it is necessary to inspect the active page tables. Implement print_mmu_range() to perform a software table walk. The utility decodes architectural attributes (cacheability, permissions, etc.) and merges contiguous mappings with identical attributes for a concise console summary. This is guarded by ARCH_ARM64_DEBUG_MMU. BUG=b:436391478 TEST=Dump and verify MMU configuration on Google/Quartz. Logs: ``` [INFO ] Dumping MMU entries for range [0x0000000000000:0x1000000000000) [INFO ] Mapping [0x0000000000000:0x0000000001000) -> PTE: 0x0000000000000000 (UNMAPPED) [INFO ] Mapping [0x0000000001000:0x0000000200000) -> PTE: 0x0040000000001403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000000200000:0x000000b000000) -> PTE: 0x0040000000200401 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x000000b000000:0x000000b018000) -> PTE: 0x000000000b000713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x000000b018000:0x000000b0e0000) -> PTE: 0x004000000b018403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x000000b0e0000:0x000000b0e8000) -> PTE: 0x000000000b0e0713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x000000b0e8000:0x000000b200000) -> PTE: 0x004000000b0e8403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x000000b200000:0x0000014600000) -> PTE: 0x004000000b200401 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000014600000:0x0000014680000) -> PTE: 0x0040000014600403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000014680000:0x00000146ac000) -> PTE: 0x0000000014680713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x00000146ac000:0x0000014800000) -> PTE: 0x00400000146ac403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000014800000:0x0000014858000) -> PTE: 0x0000000014800713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000014858000:0x000001485a000) -> PTE: 0x000000001485870f (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable [INFO ] Mapping [0x000001485a000:0x0000014a80000) -> PTE: 0x000000001485a713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000014a80000:0x0000014c00000) -> PTE: 0x0040000014a80403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000014c00000:0x0000024000000) -> PTE: 0x0040000014c00401 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000024000000:0x0000024200000) -> PTE: 0x0040000024000403 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000024200000:0x0000080000000) -> PTE: 0x0040000024200401 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Execute-Never | Non-Shareable | Device NGNRNE [INFO ] Mapping [0x0000080000000:0x000008000c000) -> PTE: 0x0000000080000713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x000008000c000:0x0000080010000) -> PTE: 0x000000008000c70f (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable [INFO ] Mapping [0x0000080010000:0x0000080200000) -> PTE: 0x0000000080010713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000080200000:0x0000081c00000) -> PTE: 0x0000000080200711 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000081c00000:0x0000081c60000) -> PTE: 0x0000000081c00713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000081c60000:0x0000081c80000) -> PTE: 0x0000000081c6070f (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable [INFO ] Mapping [0x0000081c80000:0x0000081e00000) -> PTE: 0x0000000081c80713 (PAGE) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000081e00000:0x00000e0800000) -> PTE: 0x0000000081e00711 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x00000e0800000:0x00000e2800000) -> PTE: 0x00000000e080070d (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Non-Cacheable [INFO ] Mapping [0x00000e2800000:0x0000100000000) -> PTE: 0x00000000e2800711 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0000100000000:0x0000880000000) -> PTE: 0x0000000000000000 (UNMAPPED) [INFO ] Mapping [0x0000880000000:0x0001000000000) -> PTE: 0x0000000880000711 (BLOCK) [INFO ] Attributes: Secure | Read-Write | Accessed | Executable | Inner-Shareable | Normal Cacheable (WBWAC) [INFO ] Mapping [0x0001000000000:0x1000000000000) -> PTE: 0x0000000000000000 (UNMAPPED) ``` Change-Id: I0e21e4db463b66e006dcbe85ed9415264bf18acd Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91408 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kapil Porwal
Subrata Banik
parent
99d409d3ba
commit
4b227a4aa6
3 changed files with 180 additions and 0 deletions
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@ -30,4 +30,15 @@ config ARCH_ARMV8_EXTENSION
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need to be changed unless specific features (e.g. new instructions)
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are used by the SoC's coreboot code.
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config ARCH_ARM64_DEBUG_MMU
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bool "Debug MMU table"
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default n
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help
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When enabled, the MMU table walker will dump the translation
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table entries and their attributes to the debug console during
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initialization or range configuration.
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This is useful for verifying that memory ranges (Normal, Device,
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Read-Only, etc.) are being mapped correctly in the page tables.
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endif # ARCH_ARM64
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@ -236,6 +236,171 @@ static void assert_correct_ttb_mapping(void *addr)
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== BLOCK_INDEX_MEM_NORMAL && !(pte & BLOCK_NS));
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}
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/* Decodes and prints the architectural attributes of a PTE. */
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static void print_pte_attributes(uint64_t pte)
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{
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/* Invalid/Unused entries */
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if (pte == 0 || (pte & DESC_MASK) == INVALID_DESC)
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return;
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printk(BIOS_INFO, " Attributes: ");
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printk(BIOS_INFO, (pte & BLOCK_NS) ? "Non-Secure | " : "Secure | ");
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printk(BIOS_INFO, (pte & BLOCK_AP_RO) ? "Read-Only | " : "Read-Write | ");
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printk(BIOS_INFO, (pte & BLOCK_ACCESS) ? "Accessed | " : "Not Accessed | ");
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printk(BIOS_INFO, (pte & BLOCK_XN) ? "Execute-Never | " : "Executable | ");
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uint64_t sh = pte & BLOCK_SH_MASK;
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switch (sh) {
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case BLOCK_SH_NON_SHAREABLE:
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printk(BIOS_INFO, "Non-Shareable | ");
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break;
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case BLOCK_SH_UNPREDICTABLE:
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printk(BIOS_INFO, "Unpredictable Shareability | ");
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break;
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case BLOCK_SH_OUTER_SHAREABLE:
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printk(BIOS_INFO, "Outer-Shareable | ");
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break;
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case BLOCK_SH_INNER_SHAREABLE:
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printk(BIOS_INFO, "Inner-Shareable | ");
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break;
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default:
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printk(BIOS_INFO, "Unknown Shareability (0x%llx) | ", sh);
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break;
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}
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uint64_t index = (pte >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK;
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switch (index) {
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case BLOCK_INDEX_MEM_DEV_NGNRNE:
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printk(BIOS_INFO, "Device NGNRNE");
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break;
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case BLOCK_INDEX_MEM_DEV_NGNRE:
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printk(BIOS_INFO, "Device NGNRE");
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break;
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case BLOCK_INDEX_MEM_DEV_GRE:
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printk(BIOS_INFO, "Device GRE");
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break;
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case BLOCK_INDEX_MEM_NORMAL_NC:
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printk(BIOS_INFO, "Normal Non-Cacheable");
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break;
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case BLOCK_INDEX_MEM_NORMAL:
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printk(BIOS_INFO, "Normal Cacheable (WBWAC)");
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break;
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default:
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printk(BIOS_INFO, "Unknown Memory Type Index (%llu)", index);
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break;
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}
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printk(BIOS_INFO, "\n");
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}
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/* Structure to hold the state of the last printed range */
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struct last_mmu_entry {
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uint64_t start;
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uint64_t end;
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uint64_t pte;
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const char *desc_type;
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bool valid;
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};
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/* Function to print the accumulated range and reset the state */
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static void print_and_reset_last_range(struct last_mmu_entry *last)
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{
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if (last->valid) {
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printk(BIOS_INFO, " Mapping [" ADDR_FMT ":" ADDR_FMT ") -> PTE: 0x%016llx (%s)\n",
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(uintptr_t)last->start, (uintptr_t)last->end, last->pte, last->desc_type);
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print_pte_attributes(last->pte);
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last->valid = false;
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}
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}
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/*
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* Prints the MMU entries for a given address range, merging contiguous
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* mappings with identical attributes.
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*/
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static void print_mmu_range(uint64_t base_addr, size_t size)
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{
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if (!CONFIG(ARCH_ARM64_DEBUG_MMU))
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return;
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uint64_t current_addr = base_addr;
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uint64_t end_addr = base_addr + size;
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printk(BIOS_INFO, "Dumping MMU entries for range [" ADDR_FMT ":" ADDR_FMT ")\n",
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(uintptr_t)base_addr, (uintptr_t)end_addr);
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struct last_mmu_entry last = { .valid = false };
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while (current_addr < end_addr) {
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int shift = L0_ADDR_SHIFT;
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uint64_t *pte_ptr = (uint64_t *)_ttb;
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uint64_t pte = 0;
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uint64_t mapped_size = 0;
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const char *desc_type = "UNKNOWN";
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/* Perform a table walk to find the terminal PTE and its size. */
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while (shift >= L3_ADDR_SHIFT) {
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int index = (current_addr >> shift) & ((1UL << BITS_RESOLVED_PER_LVL) - 1);
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pte = pte_ptr[index];
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if (pte == 0) {
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desc_type = "UNMAPPED";
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mapped_size = 1UL << shift;
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break;
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} else if ((pte & DESC_MASK) == TABLE_DESC) {
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if (shift == L3_ADDR_SHIFT) {
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/* At L3, TABLE_DESC (0x3) is actually PAGE_DESC */
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desc_type = "PAGE";
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mapped_size = GRANULE_SIZE;
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break;
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} else {
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/* At L0, L1, L2, it means TABLE_DESC, continue walk */
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pte_ptr = (uint64_t *)(pte & XLAT_ADDR_MASK);
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shift -= BITS_RESOLVED_PER_LVL;
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}
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} else if ((pte & DESC_MASK) == BLOCK_DESC) {
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desc_type = "BLOCK";
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mapped_size = 1UL << shift;
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break;
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} else {
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desc_type = "IMPOSSIBLE";
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mapped_size = 1UL << shift;
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printk(BIOS_ERR, "Unexpected descriptor (PTE: 0x%016llx) found!\n", pte);
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break;
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}
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}
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/* Align the start address to the beginning of the mapped block/page. */
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uint64_t start_of_mapping = ALIGN_DOWN(current_addr, mapped_size);
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uint64_t current_print_end = start_of_mapping + mapped_size;
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if (last.valid && start_of_mapping == last.end &&
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(pte & ~XLAT_ADDR_MASK) == (last.pte & ~XLAT_ADDR_MASK)) {
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/* Extend the last range */
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last.end = current_print_end;
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} else {
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/* Print the previous range */
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print_and_reset_last_range(&last);
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/* Start a new range */
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last.start = start_of_mapping;
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last.end = current_print_end;
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last.pte = pte;
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last.desc_type = desc_type;
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last.valid = true;
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}
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/* Advance current_addr */
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current_addr = start_of_mapping + mapped_size;
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if (current_addr <= start_of_mapping) {
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printk(BIOS_ERR, "Address overflow in %s!\n", __func__);
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break;
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}
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}
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/* Print the very last accumulated range */
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print_and_reset_last_range(&last);
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printk(BIOS_INFO, "\n");
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}
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/* Func : mmu_config_range
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* Desc : This function repeatedly calls init_xlat_table with the base
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* address. Based on size returned from init_xlat_table, base_addr is updated
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@ -263,6 +428,8 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
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tlbiall();
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dsb();
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isb();
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print_mmu_range(0, 1UL << BITS_PER_VA);
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}
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/* Func : mmu_init
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@ -396,4 +563,5 @@ void mmu_relocate_ttb(void)
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isb();
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printk(BIOS_INFO, "TTB relocation is complete.\n");
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print_mmu_range(0, 1UL << BITS_PER_VA);
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}
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@ -42,6 +42,7 @@
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#define BLOCK_XN (1UL << 54)
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#define BLOCK_SH_MASK (0x3 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_SHIFT (8)
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#define BLOCK_SH_NON_SHAREABLE (0 << BLOCK_SH_SHIFT)
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#define BLOCK_SH_UNPREDICTABLE (1 << BLOCK_SH_SHIFT)
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