Documentation/releases: Update release notes for 26.03 release
These are the preliminary release notes. They'll need to be updated with any changes done this week. We'll need another patch after the tag to capture the final statistics. The notes will be changed from "Upcoming release" after the tag is done. Change-Id: Id24c2d43c53db7976c98f5936d9d8866a7392ad2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91731 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
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Upcoming release - coreboot 26.03
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========================================================================
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The 26.03 release is scheduled for the end of March, 2026
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The coreboot project is pleased to announce the release of coreboot 26.03.
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This release incorporates 856 commits from 95 contributors, reflecting
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continued focus on runtime configuration, security hardening, platform
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enablement, and memory/display data reliability across supported systems.
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Key improvements include:
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- Full support for Intel PantherLake SoCs (released at CES 2026 this January)
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- Refinements to CFR-based runtime configuration, including clearer
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dependency wiring and more platform-exposed options
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- Increased SMMSTORE capacity and improved handling of mmapped SMMSTORE reads
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- TPM and signed secure blob plumbing updates across multiple platforms
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- SPD/memory data generation refresh, including JSON-based sources and
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build-time `spd.hex` generation
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- MediaTek MT8196 display pipeline improvements (DSI dual-channel support and
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panel power-off handling)
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- Storage integrity and security hardening improvements, including COREBOOT/
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BOOTBLOCK locking and CBFS verification redundancy support
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Update this document with changes that should be in the release notes.
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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* Note that all changes before the release are done are marked upcoming.
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A final version of the notes are done after the release.
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As always, the coreboot project extends our appreciation to everyone who
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contributed to this release. From experienced developers implementing
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hardware-focused platform changes to community members validating
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functionality and reporting issues, the combined effort drives the
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continued evolution of open firmware and more reliable system initialization.
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The next coreboot release, 26.06, is scheduled for the end of June 2026.
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Significant or interesting changes
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----------------------------------
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* Add changes that need a full description here
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### drivers/option/cfr: Refine and extend runtime configuration options
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* This section should have full descriptions and can or should have
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a link to the referenced commits.
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The coreboot Forms Representation (CFR) runtime option framework was
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refactored to make platform dependencies more explicit and to keep option
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selection consistent across Intel SoCs and the boards that expose CFR-based
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controls.
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Intel SoC CFR integration was simplified to use boolean dependency wiring
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instead of enum-based gating, and the option plumbing was cleaned up across
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multiple boards and variants. In addition to general stability and
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integration work, several platforms gained new CFR-exposed runtime options
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for PCIe/power configuration, input device identification, Bluetooth runtime
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configuration, and a number of firmware configuration controls used by
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payloads that support CFR-driven setup.
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### drivers/smmstore: Improve memory-mapped reads for SMMSTORE
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The SMMSTORE driver was adjusted to use `lookup_store()` for
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memory-mapped reads, improving consistency of mmapped access patterns across
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architectures and reducing the likelihood of stale mappings during runtime
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reads.
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### TPM and signed secure blobs: board wiring and common plumbing improvements
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TPM enablement received cross-platform updates that cover ACPI integration,
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PSP emulation paths, and board-specific wiring.
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ACPI received additional enums for the TPM2 start method. On Qualcomm
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platforms, logic was added to handle secure boot blob paths in support of
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signed secure blob flows (gated by new Kconfig for signed blobs). The
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AMD/PSP software stack gained support for an fTPM driver implementation for
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PSP emulated CRB TPMs.
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Several board implementations were updated to match expected TPM resource
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layouts, including moving TPM into the devicetree on Lenovo platforms and
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adding TPM I2C plus EC SPI configuration on supported ChromeOS boards.
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### Memory SPD generation refresh: JSON-based sources and LP5/LPDDR5 expandability
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SPD-related work focused on reducing the amount of manual SPD data
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maintenance while improving coverage for new memory parts.
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Starlabs platform SPD sources were converted to JSON, and the build system
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now generates `spd.hex` from these JSON inputs at build time. The SPD
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tooling also gained improvements to `spd_gen` for Make-driven builds, along
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with new SPD decode helpers used for newer LPDDR5/LP5 families.
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Additional fixes in the SPD parsing pipeline address DDR5 channel mapping and
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corner-case arithmetic issues, improving the reliability of generated memory
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configuration.
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### MediaTek MT8196 display pipeline updates (DSI dual channel, panel power-off)
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The MediaTek MT8196 display stack was extended for broader DSI topologies and
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more consistent panel power management.
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DSI support was expanded to handle dual-channel configurations, with updated
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DSI PHY control method integration. Panel command handling was extended with
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explicit power-off support via a shared panel power-off API, and the
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platform gained common low-battery power-off handling for consistent runtime
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behavior.
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These updates refine initialization sequencing and improve the timing
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interaction between boot-state based initialization and display bring-up.
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### Firmware security hardening: lockdown controls and CBFS redundancy verification
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Security and integrity controls were expanded across multiple platforms.
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Intel SoCs moved to a common PMC lockdown driver, and several platforms
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received a shared runtime control path for BIOS SMM write protection.
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coreboot also gained an option to lock COREBOOT and BOOTBLOCK contents,
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strengthening the expected tamper resistance during normal operation.
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On the storage integrity side, CBFS verification was extended with Top Swap
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redundancy support, improving robustness when payload redundancy is used as
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part of the platform update or recovery strategy.
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@ -31,7 +122,25 @@ Additional coreboot changes
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The following are changes across a number of patches, or changes worth
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noting, but not needing a full description.
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* Changes that only need a line or two of description go here.
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* Intel SPI flash robustness improvements including spinlock protection for fast
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operations and prevention of transfers across 4KiB boundaries.
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* Additional Intel SoC initialization refactoring, including common late-stage
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finalize implementation used by multiple x86 families.
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* PCIe and FSP parameter updates across several Intel SoCs, including
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platform-specific root port programming and improved PCIe power management
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configuration.
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* Panther Lake/WCL power management work, including additional power-state
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threshold configuration and PCIe clock-control support.
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* ChromeOS platform boot/power robustness improvements, including secure
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low-power charging path handling and improved behavior when charger applet
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enablement fails.
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* Display and camera pipeline fixes, including sensor SSDB validation and
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board-specific MIPI camera configuration updates where required.
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* Starlabs platform storage/power enablement including helper-based NVMe
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power sequencing and additional card reader enablement controls.
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* Qualcomm x1p42100 enablement updates including secure boot blob path logic,
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DMA/stack region adjustments, and SPI bus speed tuning.
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* RISC-V SMP correctness fixes, including resolution of a race in SMP bring-up.
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@ -40,48 +149,85 @@ Changes to external resources
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### Toolchain updates
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* Upgrade clang used by coreboot's cross toolchain build to 21.1.8.
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* Cross-compilation fixes for toolchain selection and target arguments to
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keep the build deterministic across host environments.
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### Git submodule pointers
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* `amd_blobs` submodule pointer advanced for updated AMD firmware blobs.
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* `libgfxinit` submodule bumped to a newer revision.
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* `vboot` submodule updated from the 2024 snapshot to the upstream 2026
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baseline.
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### External payloads
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* EDK2 build now generates an optional update capsule in support of UEFI update
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flows. Payload configuration updates include a new MrChromebox branch baseline
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and serial-output adjustments.
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* Depthcharge default configuration updated to use a 64-bit libpayload setup.
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* libpayload extended to pass panel power-off commands to payloads, and
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liblz4 constant definitions were exported to keep payload-side compression
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logic in sync.
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Platform Updates
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----------------
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### Added mainboards:
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* To be filled in immediately before the release by the release team
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* Intel Pantherlake CRB
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* Qotom qdnv01
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* Siemens MC EHL7
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* Siemens MC EHL8
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* Star Labs Starbook Horizon
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### Removed Mainboards
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* To be filled in immediately before the release by the release team
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### Updated SoCs
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* To be filled in immediately before the release by the release team
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Plans to move platform support to a branch
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------------------------------------------
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* To be filled in immediately before the release by the release team
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* AMD Turin POC: Added SPI TPM SoC-specific initialization and aligned Turin
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sources for the PoC platform.
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* Intel Alderlake: Dropped invalid builtin root port handling in FSP params,
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migrated to common global reset and common PMC lockdown plumbing, and
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cleaned up CFR dependency wiring.
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* Intel Cannonlake: Migrated to common global reset and standardized common
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GSPI/I2C/UART device mapping plus shared CFR boolean wiring.
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* Intel Elkhartlake: Switched to common global reset and common eSPI/LPC
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initialization with shared GSPI/I2C/UART devfn mappings.
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* Intel Jasperlake: Added IGD naming via `soc_acpi_name`, moved PCIe ModPHY
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parameter wiring into shared pcie_rp.h, standardized common global
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reset/eSPI initialization, and added an initial `chipset.cb`.
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* Intel Meteorlake: Switched to Arrow Lake FSP usage (including Arrow Lake
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microcode binaries) and migrated to shared finalize/global reset/PMC
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lockdown implementations, plus ARL-H 45W power entry support.
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* Intel Pantherlake: Tuned WCL SKU behavior (icc_max and power-state
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thresholds, TdcTimeWindow defaults, and CD clock frequency control) while
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moving the platform to shared finalize/global reset/PMC lockdown flows.
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* Intel Tigerlake: Migrated to common global reset and common PCH client
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SMI handling, standardized eSPI/LPC initialization plus shared
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SoundWire/SPI/I2C/UART device mapping, and replaced CFR enums with
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booleans.
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* MediaTek MT8196: Expanded DSI to support dual-channel configurations,
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improved display pipeline bring-up (including framebuffer sizing and MIPI
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register control), and added support for dual-MIPI logo rendering and
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common panel power-off handling.
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* Qualcomm x1p42100: Added secure boot blob path logic for signed secure
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blob support, increased SPI bus frequency (75MHz), and adjusted DMA/stack
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region layout; also extended LPASS-side APIs used for platform bring-up.
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Statistics from the 25.12 to the 26.03 release
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--------------------------------------------
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* To be filled in immediately before the release by the release team
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Significant Known and Open Issues
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---------------------------------
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Issues from the coreboot bugtracker: <https://ticket.coreboot.org/>
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* To be filled in immediately before the release by the release team
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* Total Commits: 856
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* Average Commits per day: 9.42
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* Total lines added: 107457
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* Average lines added per commit: 125.53
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* Number of patches adding more than 100 lines: 72
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* Average lines added per small commit: 41.11
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* Total lines removed: 22154
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* Average lines removed per commit: 25.88
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* Total difference between added and removed: 85303
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* Total authors: 95
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@ -94,4 +240,3 @@ coreboot Links and Contact Information
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* Documentation: <https://doc.coreboot.org>
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* Issue tracker: <https://ticket.coreboot.org/projects/coreboot>
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* Donations: <https://coreboot.org/donate.html>
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