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Doc/nb/intel/haswell: Fix typo

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Chomeboxes ---> Chromeboxes

Change-Id: Ifdd9a1374d4d021c2777694937da2c81d22004e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91760
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Angel Pons 2026-03-19 09:45:49 +01:00 • committed by Matt DeVillier
commit 0f30eed3e8
1 changed files with 1 additions and 1 deletions
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Documentation/northbridge/intel/haswell/mrc.bin.md
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@ -31,6 +31,6 @@ its location when building coreboot.
When `mrc.bin` has finished executing, ECC is active on the channels
populated with ECC DIMMs. However, `mrc.bin` was tailored specifically
for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM.
for Haswell Chromebooks and Chromeboxes, none of which support ECC DRAM.
While ECC likely functions correctly, it is advised to further validate
the correct operation of ECC if data integrity is absolutely critical.