mb/google/bluey: Initiate PCIe link training in romstage

Select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT for the Bluey board to allow
non-blocking PCIe link training.

Call qcom_setup_pcie_host() during platform_romstage_postram() when
performing a normal boot.

This takes advantage of the asynchronous PCIe initialization logic,
starting the link training early to save approximately 100ms of
blocking wait time in ramstage.

BUG=b:449871690
TEST=Able to save 100ms of the boot time (google/quenbih).

w/o patch:

```
5000:<unknown>         1,224,619 (662)
5001:<unknown>         1,324,851 (100,232)
```

w/ patch:

```
5000:<unknown>         1,098,810 (808)
5001:<unknown>         1,098,928 (118)
```

Change-Id: If758c2fb8f7a6a5bb8c5fe6c1d7b44e988858179
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/mainboard/google/bluey/Kconfig

@@ -6,6 +6,7 @@ config BOARD_GOOGLE_BLUEY_COMMON
 	# FIXME: keep ADB for development phase
 	select GBB_FLAG_ENABLE_ADB if VBOOT
 	select MAINBOARD_HAS_CHROMEOS
+	select SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT
 	select SPI_FLASH
 	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
 	select SPI_FLASH_INCLUDE_ALL_DRIVERS

src/mainboard/google/bluey/romstage.c

@@ -10,6 +10,7 @@
 #include <gpio.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/aop_common.h>
+#include <soc/pcie.h>
 #include <soc/pmic.h>
 #include <soc/qclib_common.h>
 #include <soc/shrm.h>
@@ -188,4 +189,8 @@ void platform_romstage_postram(void)
 		*boot_mode_ptr = boot_mode;
 		printk(BIOS_INFO, "Boot mode is %d\n", *boot_mode_ptr);
 	}
+
+	/* Perform PCIe setup early in async mode if supported to save 100ms */
+	if (boot_mode == LB_BOOT_MODE_NORMAL)
+		qcom_setup_pcie_host(NULL);
 }