In order to fit the specification, change gpio setting for touch panel
and wwan.
Change items:
1. wwan : Add WWAN_RST_L to 0. And we want WWAN_EN to pull high more
early than WWAN_RST_L, so add WWAN_EN to 1 in romstage stage.
2. touch panel : First we add EN_PP3300_TCHSCR and USI_RST_L to 0 to
init status. And we want EN_PP3300_TCHSCR to pull high more early than
USI_RST_L so delete USI_RST_L pull high in romstage.
BUG=b:357764679
Test=emerge-nissa coreboot
Change-Id: I0a07ea8e2bf3d165dcebd89c4c564f157d9d4846
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84668
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting devices to unprovisioned allows us to perform
functional testing without having to rewrite the fw config
during the SMT phase of factory production.
BUG=None
TEST=Build lotso firmware and boot to OS when fw_config is
unprovisioned and ensure all devices are enable.
Change-Id: I3b8285ce335ee0f3595d184eb0921f697bdbd0c2
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84714
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Since the Kconfig default for boolean options is already 'n', there's no
need to add that default to the option. Still kept the 'default n' for
the 3 options that result in fuses inside the SoC to be burnt
(PERFORM_RPMC_PROVISIONING, PERFORM_SPL_FUSING and
PSP_PLATFORM_SECURE_BOOT) to point out the fact that that's not selected
by default more clearly.
Change-Id: I55971f1f130d8ec23d4572a215008d9465e1520a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add the data structures used for the command buffers for the PSP SMI
commands to increment and request the state of the monotonic counters in
the SPI flash. These data structures are specific to the PSP SMI mailbox
interface and not the data structures from the RPMC specification. The
AGESA code was used as a reference.
Change-Id: I8bc8ff4cf9b7ebd0e034f040dde2db8385bb8f79
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes:
pcieport 0000:00:06.0: can't derive routing for PCI INT D
pcieport 0000:00:06.0: PCI INT D: not connected
PEG1 should also be PCI_INT_B.
Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.
Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Windows driver only checks PCI0, so move the window accordingly
so that it can be used.
Tested on `starlite_adl` by booting Windows 11 installation medium.
Prior to this patch, it would flag that the security requirements
were not met - it now happily installs.
Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This pin is used by the DisplayPort connector for Hot Plug.
Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override the PL4 to the maximum power the battery can provide
without a charger connected to prevent drawing too much power.
Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The wrong definition was used, so the code had no effect.
The ID for the processor used is `b06e0`.
Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards use hubs for devices, so correct the ACPI configuration
for these ports. Also, add more information to the comments for the
ports.
Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Make the I2C speed user configurable from CMOS. Both the touchscreen
and accelerometer support running at 100MHz or 400MHz. They perform
better at 400MHz but use more power - this patch lets the user choose.
Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This method is used to provision the CNVi, and ensure
that it is in the correct state.
Intel document #559910 details this.
Change-Id: Id8a36a09c7beaf3ba8b29d3276bd9dc59420dab5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83713
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method is used to limit frequencies on CNVi.
Intel document #559910 details this.
Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must
exist to avoid a BSOD on Windows.
Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add a general purpose handle to allow CNVi to be notified
of state changes.
Intel document #559910 details this.
Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a _PRR method that the OS can use to reset the wireless.
This is only used for integrated solutions and depends on the
CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new
ACPI is added, the behavior of existing boards won't be
changed unless they configure the accompanying Bluetooth device.
Intel document #559910 details this.
Change-Id: I25e8462780badcad88b13052a6eb282c83af5def
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
All CNVi modules, integrated or dedicated only support D3 Hot
so add _S0W to limit the sleep state.
Intel document #559910 details this.
Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
These fields are used to monitor events on CNVi.
Intel document #559910 details this.
Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
The CNVi driver is relatively basic in coreboot and most
noticeably, recent Linux kernels flag that lack of a _PRR
method, which is used to reset WiFi and Bluetooth.
This patch series adds methods recommended by Intel in
document #559910.
This patch defines an OpRegion for CNVi, for both
integrated and dedicated solutions.
Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook up CNVi Bluetooth UPDs to the devicetree. Set CnviBtCore to
`true` so the current behaviour is not changed.
Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84596
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of these boards support or use S0ix so c6dram isn't needed, so
disable it.
Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is only 1 Type-C port, the rest are Type-A.
Tested on Linux by verified the correct names are shown in dmesg.
Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Port 2 is a hub, used for the internal keyboard and the card reader.
Adjust this to a hub.
Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
The existing GPIO configuration was IRQ heavy; tweak this to reduce
the number of interrupts.
Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A debug configuration was left in the patch when it was uploaded,
remove this.
Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
The wireless GPIOs don't need to be configured in the bootblock,
so set them up in ramstage.
Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The first table from the chapter 4.1 'OP1/OP2 Command Definition: No
Address Phase' of the JEDEC standard JESD260 (Replay Protected Monotonic
Counter (RPMC) for Serial Flash Devices) in the version from April 2021
was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0050aea6cdc537122bae63fddb417dd9f6b75a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the case where the x86 owns the SPI controller and the RPMC feature
is used, the PSP will send an SMI to the x86 side for it to send the
RPMC increment monotonic counter and RPMC request monotonic counter
commands to the SPI flash and return the result to the PSP. Add stubs
as handlers for those two PSP SMI commands.
Change-Id: If6091d2b0002f817922cac4cba373f0f981b646e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84702
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Cabral
STMicro first moved their SPI NOR flash business to Numonyx which was a
joint venture with Intel which later got sold to Micron, so add a
comment to the VENDOR_ID_STMICRO JEDEC manufacturer ID define and
mention all 3 companies that have sold SPI NOR flash chips using this
manufacturer ID to the Kconfig help text of SPI_FLASH_STMICRO.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7886396d8f0a9766f568a221c0b5ade02489060b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84018
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This change updates the EC event parameters for Ovis, a Chromebox.
As a result, several existing parameters like LID, battery, and AC
connect/disconnect are no longer applicable to the Chromebox design.
TEST=Successfully built and booted google/ovis.
Change-Id: I2b9a6970a07624e16b4483907b8d2b77c04d535c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84671
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meteor Lake handles a misconfigured devicetree better than Alder Lake
and Tiger Lake; it throws a warning and corrects the FSP config rather
than asserting.
Copy that behavior to Alder Lake and Tiger Lake.
Change-Id: Ifd768fc31a0a6ef2fa0ae7e890cf0b47a9968d30
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84647
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Since version 6.6, Linux has warned about the lack of a
_PRR Method being available for Intel Bluetooth. Add one
that follows the recommendations from Intel in their
connectivity integrated guide, that uses the reset
delay set by the DSM.
Change-Id: I9c7fd286e8630d77d79d1d7cd113ce3a3d3d0fe3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84145
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel Bluetooth driver can be combined with either CNVi, or
full PCI wireless cards such as the AX210. Move it to the USB
code so it can be used by either or.
Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code for Intel Bluetooth is unrelated to all other devices, and
needs to grow in size - move it to another file.
Change-Id: I65ccb9f2fd95b07fa63866485920539adc474873
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84625
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 8cfe1b3302 (mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13): CB:84124, changes the fingerprint IRQ pin from GPP_F15 to GPP_D13, but forgot to update the pin in the array fp_disable_pads.
Hence update fp_disable_pads configuration to include that GPIO.
BUG=None
TEST= build firmware
$ emerge-brox coreboot
Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84545
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Currently, building edk2 with coreboot will show multiple error
prints:
!!!!!!!! Image Section Alignment(0x40) does not match Required Alignment (0x1000) !!!!!!!!
Adjust the definations so these are aligned to 0x1000.
Change-Id: I881bfd1eec55454e444909b845a342a94ba8904b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add helper function to allow platform to fill gicc parameters for use in
ACPI table.
Change-Id: Ibd4c52a5482707fae8aa1b8b21fdc6bb5f4b45c2
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79973
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
