mb/starlabs/starlite_adl: Alphabetize and group FSP UPDs

Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb

@@ -8,13 +8,11 @@ chip soc/intel/alderlake
 		},
 	}"
 
-	# FSP Memory
-	register "sagv"				= "SaGv_Enabled"
-
-	# FSP Silicon
-	register "eist_enable"			= "true"
-	register "cnvi_bt_core"			= "true"
+	# FSP UPDs
 	register "cnvi_bt_audio_offload"	= "true"
+	register "cnvi_bt_core"			= "true"
+	register "eist_enable"			= "true"
+	register "sagv"				= "SaGv_Enabled"
 
 	# Serial I/O
 	register "serial_io_i2c_mode" = "{