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soc/intel/cnvi: Add CWAR Fields

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These fields are used to monitor events on CNVi.

Intel document #559910 details this.

Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This commit is contained in:
Sean Rhodes 2024-07-31 20:23:41 +01:00
commit 9394bace4e
1 changed files with 18 additions and 0 deletions
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18
src/soc/intel/common/block/cnvi/cnvi.c
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@ -68,6 +68,24 @@ static void cnvw_fill_ssdt(const struct device *dev)
acpigen_write_field("CWAR", fields, ARRAY_SIZE(fields),
FIELD_WORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
/*
* Field (CWAR, ByteAcc, NoLock, Preserve)
* {
* Offset (0xcd),
* PMEE, 1,
* , 6,
* PMES, 1
* }
*/
struct fieldlist fields2[] = {
FIELDLIST_OFFSET(0xcd),
FIELDLIST_NAMESTR("PMEE", 1),
FIELDLIST_RESERVED(6),
FIELDLIST_NAMESTR("PMES", 1),
};
acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2),
FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE);
acpigen_write_scope_end();
}