erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/alderlake: Fix PEG0 IRQ routing

Browse source 
PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes:
    pcieport 0000:00:06.0: can't derive routing for PCI INT D
    pcieport 0000:00:06.0: PCI INT D: not connected

PEG1 should also be PCI_INT_B.

Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.

Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2024-10-02 12:12:00 +01:00
commit 542dd2e4e6
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/alderlake/fsp_params.c
View file

@ -98,8 +98,8 @@ static const struct slot_irq_constraints irq_constraints[] = {
{
.slot = SA_DEV_SLOT_CPU_6,
.fns = {
FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A),
FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C),
FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_D, PIRQ_A),
FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_B, PIRQ_C),
},
},
{