Introduce the lb_panel_poweroff/cb_panel_poweroff structs to pass the
panel power-off commands from coreboot to payloads.
Also add mipi_panel_parse_commands() to libpayload libc, so that
payloads can utilize it to parse the power-off commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I652178c8075a1f3aee356502e682ef9a4f3d1cf8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the trace length for the card reader USB port, and based on this
value adjust the macro used accordingly.
Change-Id: I1c7661f492b9193b75ed39abb2f5d14614cfc213
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `card_reader` option is only available on specific boards,
so to avoid enabling a USB port that isn't connected, set the
fallback value to 0 instead of 1.
Change-Id: Ied540d6242758663db7a7a11fbefb5c4a84b942d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90770
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support for the Ibex Peak chipset was added in commit 888d559b03
("Support for Ibexpeak southbridge") by copy-pasting the bd82x6x
implementation and making appropriate changes. This resulted in some
of the PCI IDs for 6/7 series chipsets being left behind.
While some of these PCI IDs were removed in a commit b7d8788880
("ibexpeak/lpc: Fix PCIIDs."), there are still some that remain, we
remove those in this commit.
Change-Id: I5dc0e4fb2694eec9ef6246e0ae9211dff604d5b9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89569
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This update introduces support for Google touchscreen devices
to the existing framework, enhancing compatibility with Google's
hardware interfaces. It extends the fw_config field with new
options to accommodate different connection types used by Google
touchscreens. Specifically, it adds:
- TOUCHSCREEN_LPSS_I2C_ELAN_REX for ELAN9006 interfaced via LPSS-I2C.
- TOUCHSCREEN_THC_SPI_ELAN_REX for ELAN6918 interfaced via THC-SPI.
- TOUCHSCREEN_THC_I2C_ELAN_REX for ELAN9006 interfaced via THC-I2C.
BUG=none
TEST=Connect Google's REX touchscreen with the conversion cables. Boot
to OS with fw_config setting for Google's touchscreen and verify
device enumeration in /sys/bus/hid/devices directory.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3fda0e4587d8484881c844674053a0badfc23a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89181
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard no SATA interface is assembled. Therefore, it is
deactivated.
TEST=Boot into OS and verify via lspci if relevant SATA Controller is
deactivated and no error in coreboot log is shown.
Change-Id: Iea01c30d18d81e67087ac8abef5cece0040087e5
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90730
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the unused GbE and PSE TSN GbE device 0. These devices are not
required for the current board functionality. Removing them simplifies
the configuration.
Also PSE is not used for any other functionality, the local host
interface is deacitivated as well.
TEST=Check if all other GbE ports of mainboard still work.
Change-Id: I83c7e9731d3684a0b0a7f16b533ee3ea2989f3c6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90726
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add AX211 wifi sar table for gothrax wifi sar config.
Use fw_config to separate different wifi card settings.
WLAN_AX211_Intel: 1
BUG=b:454207611
Test=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I11cf6cd61a13f5365530fc07b589d749c9459d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
`VBOOT_EARLY_EC_SYNC` enables EC software sync in romstage.
This is useful to achieve full USB-PD negotiation early in the boot
flow. It eliminates a problem where PMC is wrongly configured in
depthcharge during the EC-sync scenario which prevents USB devices
from getting detected when connected via a self-powered USB hub.
`VBOOT_EC_SYNC_ESOL` displays early sign-of-life (eSOL) during EC
firmware updates.
BUG=b:386920751,b:467506959,b:468885646
TEST=Verify detection and booting to OS from USB drive connected to
the Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Verify that eSOL is displayed during EC firmware update.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I612b4dc13be2efaee863e6cacf8fc4c432edc313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90762
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Relocate the CBMEM top address from a hardcoded 0xC7800000 to the
start of the XBL log region (_dram_xbl_log).
This change moves the CBMEM region from the high Linux Kernel Reserve
block down into the lower DRAM Space 0, adjacent to other firmware
reserved regions. This consolidation prevents marking CBMEM range as
`reserved` and ensures CBMEM is placed in a more stable memory location
(marked available aka System RAM).
- Remove CBMEM_TOP define from addressmap.h.
- Update cbmem_top_chipset() to return (uintptr_t)_dram_xbl_log.
- Update memlayout.ld documentation to reflect the new memory map.
BUG=none
TEST=Boot on X1P42100 platform, verify CBMEM console and tables are
accessible and correctly located via 'cbmem -l'.
w/o this patch:
```
c7800000-cb7fffff : reserved
```
w/ this patch:
```
815a0000-819fffff : System RAM
```
Change-Id: I7392bb7a62d50640696301931940a7baa00351e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90760
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("S5VM17" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Ubuntu 25.10) on google/redrix, verify MIPI
camera functional under both OSes using the Intel IPU6 driver stack.
Change-Id: Ic72a96e93706c096b3839ab4c951e1d0a725b5ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90744
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("CJFLE23" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Arch) on google/kano, verify MIPI camera
functional under both OSes using the Intel IPU6 driver stack.
Change-Id: I9232318c30ba0eee6dcd54f7199f6995a8ffa48b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90743
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As there is no model of the X280 with a dGPU, its devicetree does not
declare a device with a dgpu alias like the other Skylake/Kaby Lake
Thinkpad ports. This breaks the DEV_PTR(dgpu) reference in cfr.c,
causing the following build error if CONFIG_DRIVERS_OPTION_CFR is set:
In file included from src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:9:
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c: In function 'update_dgpu':
build/static.h:11:33: error: '_dev_dgpu_ptr' undeclared (first use in this function); did you mean '_dev_igpu_ptr'?
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
build/static.h:11:33: note: each undeclared identifier is reported only once for each function it appears in
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
make: *** [Makefile:431: build/ramstage/mainboard/lenovo/sklkbl_thinkpad/cfr.o] Error 1
Fix this by declaring a WEAK_DEV_PTR for the dgpu device, which will be
overridden by the compiled devicetree if the board variant declares a
dgpu device in its overridetree.
TEST=X280 builds successfully with the following defconfig:
CONFIG_VENDOR_LENOVO=y
CONFIG_BOARD_LENOVO_X280=y
CONFIG_DRIVERS_OPTION_CFR=y
Change-Id: I18cc18a88851bb943de8ab6d2d1fdcbf0f4aea86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90674
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a hooks that will populate mem_info structure with DIMM data
obtained from OpenSIL. As the memory population may be SoC-specific,
call a SoC-specific hook to fill the data.
Change-Id: I0b489c685877ac56f45e0e3abd0bd1b64549585b
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a Kconfg option to allow the SoC to add vendor specific
BERT entries, not yet defined in the ACPI spec. The function
only has to return the size of payload data and the generic
code will allocate space on the BERT table.
The caller must fill in all BERT fields since the generic
code doesn't know anything about the BERT entry.
Change-Id: I361700098ce1a3cc6acae991456a1901d2f07fb6
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90639
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 292d7b9d3d.
The resume failure is caused by the improper DEVAPC setting in fsp_init
for DM/PM and SPM. If fsp_init runs prior to dpm_init and spm_init, it
requires AP to grant the access to DM/PM and SPM from DEVAPC. The fix is
done in CB:90756.
BUG=b:474254985
TEST=Run suspend/resume test
Change-Id: Id21327f6d65d31659cdb8b4bda3b0a0510c438e8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Modify the Wacom digitizer HID to support the Samsung S-pen. This allows
a different driver to attach under Windows, which adds support for the
side buttons as eraser function and air command.
TEST=build/boot kahaku, verify S-pen works under Windows/Linux
Change-Id: I60b75f7f16f6bb028ad1747e78cc49cac810fc92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90735
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no wifi_mtcl.bin file publicly available, nor can it be
extracted from the stock Google firmware for YAVIKS, so restrict
USE_MTCL to downstream ChromeOS builds since validate_mtcl() fails
when no file is present in CBFS.
TEST=build/boot yaviks, verify no MTCL error in cbmem
Change-Id: I450db6fd8c460109aa4e491d88ec874c5f6429d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
All cyan-based boards define the size of the BIOS region in their IFD
as 6MB in size; it is likewise defined as such in chromeos.fmd. To
avoid having to override this in the board's config file when building
with a modern payload like edk2, set the default CBFS_SIZE to 6MB as
well to avoid issues with the payload not fitting.
TEST=build/boot google/edgar w/edk2 payload and default CBFS_SIZE
Change-Id: I17122aa2eb9848799c284d13d8c903ad125092b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90733
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CFR support was added in commit c1f0be39da ("mb/google/zork:
Add CFR option menu support"), a comma was inadvertently left off
the end the first CFR object in the list, which breaks compilation.
Fix this by adding the missing comma.
TEST=build/boot zork
Change-Id: I5f13d87cbc81f440b0c14d253a6334adab45631e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90732
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used the logical OR (||) operator to select
between config->tdp and get_cpu_tdp(). In C, the || operator returns a
boolean value (0 or 1), not the value of the first true operand. This
caused the function to return incorrect TDP values.
This commit replaces the logical OR with the ternary operator (?:),
ensuring that config->tdp is returned if it is non-zero; otherwise,
get_cpu_tdp() is used. This change restores the intended behavior of
selecting the correct TDP value.
TEST=The power map is properly found and applied on a Panther Lake B005
SoC.
Change-Id: I3a02f804510f87cb4d28bd929869570c355c5242
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90759
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add and enable IOST feature to support Intel's IO Self-Testing Software
(IOST), which is an OS tool for performing electrical margining analysis
on USB4 Host and Device Routers, DP2.1 displays, memory, UFS, and PCIe
Gen4+ devices. This change includes the IOST ACPI device in the SoC's
southbridge ASL and implements the SoC-specific soc_fill_p2sb_ssdt
function used by the common P2SB code to generate ACPI code for enabling
IOST in the DSDT. Additionally, the CBFS option "iost_enable" is
required to enable IOST. Command to add this option to the image:
cbfstool <coreboot_image> add-int -r COREBOOT -i 1 -n option/iost_enable
Note that this cbfstool command is an example, for its syntax format
could be changed in the future versions.
BUG=none
TEST=Build coreboot and add the CBFS option flag to the built image.
Boot to OS and verify IOST can access P2SB registers through the ACPI
interface for electrical margining tests.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I6929fa3a44646c5385199a8b1e3d0b681d36c9cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add ACPI device for Intel's IO Self-Testing Software (IOST), which is an
OS tool for performing electrical margining analysis on USB4 Host and
Device Routers, DP2.1 displays, memory, UFS, and PCIe Gen4+ devices.
This ACPI device provides the necessary P2SB access interface to enable
IOST to interact with hardware registers for comprehensive IO testing
and validation. The ASL file should be included in the SoC's
southbridge.asl.
BUG=none
TEST=Build coreboot with this ASL file included in the SoC's
southbridge.asl. Boot to OS and verify IOST objects appear correctly in
the DSDT tables.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9417da8322931c2afbf75aa9062bceb52b8320d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90128
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add weak function to fill SSDT for SoC-specific P2SB extensions. SoCs
can implement this function to fill additional P2SB-related ACPI
objects. For instance, a SoC might include the IOST ACPI interface that
uses P2SB and enable it via SSDT for debug purposes at the OS level.
BUG=none
TEST=This change cannot be tested in isolation as it only adds an empty
weak function. Testing requires SoCs to implement the function. Add the
necessary code with the same function name in the SoC to generate ACPI
objects and examine the SSDT for changes after boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I352f13b9b05dc4b61608a33c76946883bf0d3de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add CPUID definition and CPU table entry for Intel Nova Lake processor
(CPUID 0x300f30). This enables basic CPU initialization and
multiprocessor support for Nova Lake platforms
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: Iea89ebfa8bae3448edfb3b757443ec9902cede5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Based on the "TCG ACPI Specification" Version 1.3 published 2021.
Add an enum for the ACPI start methods and use it instead of hardcoding
various numbers in plain code.
Change-Id: I8b66527ee7417e231fe52e0a609b8c100de522b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89458
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The AMD fTPM uses the CRB interface, but doesn't implement all registers
defined in the TCG specification. Add a new driver that deals with the
reduced register set.
The reduced CRB MMIO register space has:
- A START register to ring the doorbell
- An error STATUS register with only one bit
- DMA address and size register for the CRB
- No other status or control registers
- No way to read current locality (assumption is locality 0)
- No interface ID register
- No read only registers
The TPM interface also assumes that the DRTM is always using locality 0.
The fTPM needs to access the SPI flash and this is currently done using
the PSP SMI handler. Thus the fTPM will only operate after SMM has been
set up.
The fTPM needs the PSP directory files type 0x04 and type 0x54. When
the regions are missing or corrupted the fTPM won't be operational.
Based off https://github.com/teslamotors/coreboot/tree/tesla-4.12-amd
TEST=Works on AMD glinda (Fam 1Ah).
This adds the following new log messages:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM: CRB buffer created at 0x7b5ee000
[SPEW ] fTPM: CRB TPM initialized successfully
[INFO ] Initialized TPM device fTPM
...
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM2 log created at 0x7b5b1000
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] ACPI: * TPM2
[DEBUG] ACPI: added table 4/32, length now 68
Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update the PS1 threshold values for VR_DOMAIN_IA, VR_DOMAIN_GT, and
VR_DOMAIN_SA from 20 A to 15 A, following the recommendations in the
Panther Lake H Platform Design Guide (Draft > 2.1). This change ensures
that power state thresholds are consistent with the most recent platform
specifications, improving accuracy and system behavior under varying
power conditions.
TEST=Fatcat device boots to OS.
Change-Id: I358d4d94c3800ff5b658cb875c90ee7409d86377
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the board to perform a hardware reboot when the TCO watchdog
expires. This is achieved by using the default Kconfig option
SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN with 'n'.
TEST=Verified in the OS on mc_ehl7:
Checked IO-mapped register 0x408 Bit 0.
Without this patch, the bit is 1 (No Reboot enabled).
With this patch, the bit is 0 (Reboot on expiry enabled).
Change-Id: If3bee9db84c92480762f8a802031d2b01541dbdb
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
On this mainboard no RTC is assembled. Therefore, it is deactivated.
TEST=Boot into OS and verify if relevant I2C Controller is disabled and
no error in coreboot log is shown.
Change-Id: I23b4a735a09686fa2636280d7b410db59d884c49
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This new mainboard variant for the Siemens mc_ehl6 is initially based on
a direct copy of the mc_ehl6 configuration. This commit contains the
basic board setup with only minimal changes to enable the new variant.
Further specific adaptations for the mc_ehl7 hardware will be handled
in subsequent commits.
TEST=Build and boot to OS on mc_ehl7.
Change-Id: I46148492f65630175abb3ce884261d098314f2bc
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90714
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new Kconfig option to the ocelot mainboard
to enable VGA mode 12 support for early Sign of Life (eSOL).
- This option, `OCELOT_VGA_MODE12_SUPPORT`, is dependent on
`FSP_UGOP_EARLY_SIGN_OF_LIFE`.
- It selects `ROMSTAGE_VGA` and `FSP_VGA_MODE12` to enable the
necessary VGA components.
BUG=None
TEST=Verify VGA text rotation on ocelot RVP.
Change-Id: I71dff6e58c3e4487079c0090848ecde9da5153d7
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90731
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, Linux is unable to load the ISH firmware,
as GPP_F10 define lost
Update gpio pins GPP_F10 for ISH
bug=b:465776760
TEST=Flash and boot to OS on ocicat,
Verified ISH fw load in cpu console using below command.
~ # dmesg | grep ish
output:
intel_ish_ipc 0000:00:12.0: ISH loader: load firmware:
intel/ish/ish_wcl.bin
Change-Id: I4642560d3b14560e93158d1d19b496e22811600c
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90708
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the define for "Secondary PCI Express Extended
Capability" and move it close to the other existing defines.
Cosmetic change. No functionality was changed.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3b1ce6820f508661d3241c36c90febe0c73b7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It is needed in a later commit that is not upstream yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I260dcf199178d28387e7af06c6fb0b03c97c4bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90692
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some payloads such as depthcharge need to run MIPI panel power-off
commands before booting to the kernel. Otherwise, the abnormal power-off
timing would prevent the pixel charge from being cleared before
power-off, leading to the risk of LCD overpotential hence resulting in
image stickiness or flicker upon restarting.
Therefore, add a 'poweroff' field to the panel_serializable_data struct,
which, in a follow-up patch, will be passed to payloads for running the
power-off commands. Each MIPI panel can define the power-off commands in
that field.
As both init and power-off commands are supported, remove "_init" from
related structs and enums.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I1a7c0a14d5c197a0887a26269e4c36e498e8b7ae
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90737
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Move the MIPI panel init command parsing function
mipi_panel_parse_init_commands() and related macros and structs from
drivers/mipi/ to commonlib/mipi/, so that the function can be shared
with payloads.
In a follow-up patch, a 'poweroff' field will be added to the
panel_serializable_data struct and then passed to payloads, so that
payloads can utilize mipi_panel_parse_init_commands() to run the panel
poweroff commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I19011669f03d060e9f030b673687cbe5965d7e2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Rename `fill_lb_framebuffer` to `get_lb_framebuffer` to better
reflect that it returns framebuffer information.
The new `get_lb_framebuffer` returns a constant pointer to the
framebuffer structure instead of filling a provided structure.
This simplifies the API and avoids an unnecessary memory copy.
The file `edid_fill_fb.c` is renamed to `framebuffer_info.c`
to better match the function it now contains.
Call sites in `coreboot_table.c` and `render_bmp.c` are
updated to use the new API.
TEST=emerge-tanjiro coreboot; check the FW logo is correctly drawn.
BUG=b:319511268
Change-Id: I8d7b20a0524b6bc9fff9e6461fa0c253345df790
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90725
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits,
allowing MCHBAR to be set above 4GB (up to 42 bits).
Reference: Section 10.3 in 850519
BUG=none
TEST=boot to OS with ACPI debug enabled and check GMHB log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I885ff64598367ddadcec05926af3556024b61250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
AMD systems support 8-bit IOAPIC IDs. Some silicon initialization code
modules, like OpenSIL, may allocate an 8-bit ID by default. To respect
that configuration or set ID properly in coreboot, whole 8-bit ID field
has to be cleared and set.
Add new IOAPIC_8BIT_ID Kconfig option to allow setting 8-bit long IOAPIC
IDs.
TEST=Set IOAPIC IDs starting with 240 on Gigabyte MZ33-AR1.
Change-Id: Ie85b2272b0bc64a95d76c5677816941f1334901d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Introduce a centralized helper function, dt_add_reserved_memory_region,
to simplify the creation of sub-nodes under /reserved-memory.
Currently, various features (such as pKVM, ramoops, and platform-
specific firmware reservations) manually handle the creation of
reserved memory nodes. This involves repetitive logic for:
- Navigating or creating the /reserved-memory parent path.
- Calculating cell sizes for 'reg' properties.
- Manually adding 'no-map' or 'compatible' properties.
This helper abstracts those steps into a single call, reducing
boilerplate and the risk of cell-size mismatches across the codebase.
The function handles:
- Node creation if the path doesn't exist.
- Optional 'compatible' string assignment.
- Automatic 'reg' property generation using appropriate address/size
cells.
- Optional 'no-map' property assignment via a boolean flag.
Change-Id: Ie58f5fdcfd1863b41c177b63ed9fc25d6d220e3a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90713
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Based on the WiFi firmware configuration to add function for
getting WiFi SAR cbfs filename.
BUG=b:460231264
TEST=Build and check the system could boot to OS, and check the SAR table could work fine.
Change-Id: Ieec65debdc9f506e779352fcf8e54daa9296c0f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90376
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ICH SPI controller fails when a single transfer spans a 4KiB
boundary. Limit data_length in spi_ctrlr_xfer() to stay within the
current 4KiB page when with_address is true, avoiding the hardware
limitation at the platform driver level.
This fixes SPI read errors observed on SandyBridge, IvyBridge, Haswell,
and Broadwell when reading option variables stored in SMMSTORE. When
scanning the store to locate a given variable, reads would often cross
into the next 4KiB page (eg, reading 60 bytes from 0x313ff0).
TEST=build/boot stumpy, link, beltino, jecht boards, verify no SPI read
errors in cbmem, CFR options work properly.
Change-Id: I73d9c0acdbbb2faf5caff1f73049bff900774156
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90689
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The smmstore_lookup_region() function was using
fmap_locate_area_as_rdev_rw() directly, which only provides
direct SPI access. This bypassed the optimized lookup_store()
function that uses incoherent_rdev to enable memory-mapped
reads via the read-only device while keeping direct SPI writes
via the read-write device.
Change smmstore_lookup_region() to call lookup_store() instead,
enabling memory-mapped reads for the public API and matching
the behavior of the internal implementation.
This improves read performance for EFI options and other
consumers of the SMMSTORE region device. It also fixes an issue
where direct SPI reads were crossing 4k page boundaries on older
platforms (Broadwell and earlier) causing them to fail and the
fallback option to be used, leading to a disconnect between the
user-selected option and device beahvior.
TEST=build/boot google/guado, verify all CFR options work properly
and no errors in cbmem.
Change-Id: I34947be932ede19a3fe896fe0da6373035fe6db7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 14a7a2315e.
Reason for revert: The change causes DUT failed to resume from S3.
BUG=b:474254985
TEST=Wake up DUT by power key.
Change-Id: I2f2291a12d9b440d000a28e38bb590bc77a02c8a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The number of MCAX register used inside an MCA BANK changed from phoenix
onwards. Since phoenix all 16 MCAX register are used inside an MCA bank.
According to spec:
The MCA_SYND register stores a syndrome associated with the error logged
in MCA_STATUS or MCA_DESTAT. The “syndrome” may include syndrome values
associated with an error correcting code or other information about the
error. The contents of this register are valid if MCA_STATUS[SYNDV] bit
is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1.
source: AMD64 Architecture Programmers Manual Rev 3.42
Change-Id: I20a31776d4b031c810ef0dc6502c421ade6f4315
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the SoC USB driver to invoke mainboard_usb_typec_configure for
both primary and secondary ports. This is called after the QMP PHY
initialization to ensure the external signal path is correctly
muxed for the detected orientation.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 00001203 00000000 00000000 00000000 ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000 ................
0a600430: 00001203 00000000 00000000 00000000 ................
```
Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
