device: Rename PCI_EXP_SEC_CAP_ID -> PCI_CAP_ID_SEC_PCIE

Rename the define for "Secondary PCI Express Extended
Capability" and move it close to the other existing defines.

Cosmetic change. No functionality was changed.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3b1ce6820f508661d3241c36c90febe0c73b7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2025-09-17 14:37:01 +02:00 committed by Felix Held
commit f2788e963f
2 changed files with 2 additions and 2 deletions

View file

@ -692,7 +692,7 @@ static void clear_lane_error_status(struct device *dev)
u32 reg32;
u16 pos;
pos = pciexp_find_extended_cap(dev, PCI_EXP_SEC_CAP_ID, 0);
pos = pciexp_find_extended_cap(dev, PCI_CAP_ID_SEC_PCIE, 0);
if (pos == 0)
return;

View file

@ -204,6 +204,7 @@
#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
#define PCI_CAP_ID_PCIE 0x10 /* PCI Express */
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define PCI_CAP_ID_SEC_PCIE 0x19 /* Secondary PCI Express Extended Capability */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
@ -481,7 +482,6 @@
#define PCIE_EXT_CAP_SRIOV_ID 0x0010
/* Secondary PCI Express Extended Capability Structure */
#define PCI_EXP_SEC_CAP_ID 0x19
#define PCI_EXP_SEC_LNK_CTL3 4 /* Link Control 3 */
#define PCI_EXP_SEC_LANE_ERR_STATUS 8 /* Lane Error Status */