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mb/siemens/mc_ehl7: Deactivate GbE and PSE GbE 0

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Remove the unused GbE and PSE TSN GbE device 0. These devices are not
required for the current board functionality. Removing them simplifies
the configuration.
Also PSE is not used for any other functionality, the local host
interface is deacitivated as well.

TEST=Check if all other GbE ports of mainboard still work.

Change-Id: I83c7e9731d3684a0b0a7f16b533ee3ea2989f3c6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90726
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Uwe Poeche 2026-01-12 09:47:44 +01:00 • committed by Matt DeVillier
commit 5f76f78383
2 changed files with 0 additions and 40 deletions
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2
src/mainboard/siemens/mc_ehl/variants/mc_ehl7/Kconfig
View file

@ -5,8 +5,6 @@ if BOARD_SIEMENS_MC_EHL7
config BOARD_SPECIFIC_OPTIONS
def_bool y
select DRIVER_INTEL_I210
select DRIVERS_ETH_PHY_M88E1512
select EHL_TSN_DRIVER
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select NC_FPGA_POST_CODE

38
src/mainboard/siemens/mc_ehl/variants/mc_ehl7/devicetree.cb
View file

@ -186,46 +186,8 @@ chip soc/intel/elkhartlake
device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0
# Enable external Marvell PHY 88E1512
chip drivers/net/phy/m88e1512
register "configure_leds" = "true"
# LED[0]: On - 1000 Mbps Link, Off - Else
register "led_0_ctrl" = "7"
# LED[1]: On - 100 Mbps Link, Off - Else
register "led_1_ctrl" = "7"
# LED[2]: Blink - Activity, Off - No Activity
register "led_2_ctrl" = "4"
# INTn is not routed to LED[2] pin
register "enable_int" = "false"
register "downshift_cnt" = "2"
device mdio 0 on # PHY address
ops m88e1512_ops
end
end
end
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1
device pci 1e.4 on # PCH Time-Sensitive Networking GbE
# Enable external Marvell PHY 88E1512
chip drivers/net/phy/m88e1512
register "configure_leds" = "true"
# LED[0]: On - 1000 Mbps Link, Off - Else
register "led_0_ctrl" = "7"
# LED[1]: On - 100 Mbps Link, Off - Else
register "led_1_ctrl" = "7"
# LED[2]: Blink - Activity, Off - No Activity
register "led_2_ctrl" = "4"
# INTn is not routed to LED[2] pin
register "enable_int" = "false"
register "downshift_cnt" = "2"
device mdio 1 on # PHY address
ops m88e1512_ops
end
end
end
device pci 1f.0 on # eSPI Interface
chip drivers/pc80/tpm