Add eDP panel power-on sequences and initialize the display in the
ramstage. Also Set display registers to normal mode if initialization
flow is skipped to prevent abnormal behavior.
BUG=b:400886838,b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x39, and check the firmware
screen.
utility gbb --set --flash --flags=0x0, and check the DUT screen.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: I09edceefee9c17ce18681b85da8ca75f65ed2876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extract code for disabling secure mode from mtk_ddp_init and implement
it as mtk_display_disable_secure_mode(). This allows disabling display
secure mode without using DDP, for example, when FW display is not
needed.
Unlike previous SoCs, MT8189 is designed so that access to display
registers defaults to secure mode, due to specific product requirements.
However, Chromebook products do not use this setting and instead require
the register permissions to be set for normal mode access, consistent
with previous SoC behavior.
Also reordered function declarations to group similar types (e.g.,
display, DDP) together for better readability.
BUG=b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x0, and check the DUT screen.
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ic378ef62540c408ccd59e482abfe9f9c8ca5a13d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add support to enable QUPV3, QSPI and GPLL0 clocks. Modify
XO Source clock frequency value to 19.2KHz. The register
details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100
Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.
Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the EC host command range configuration for Ocelot
board variants, ensuring that each variant uses the correct range based
on its specific EC.
BOARD_GOOGLE_OCELOTMCHP and BOARD_GOOGLE_OCELOTMCHP4ES uses Microchip
EC.
BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOT4ES uses Nuvoton EC.
BOARD_GOOGLE_OCELOTITE and BOARD_GOOGLE_OCELOTITE4ES uses ITE EC.
Key changes:
- Microchip EC: Configured to use host command ranges 0x800-0x807 and
0x200-0x20f. The register is set to 0x00040801 to accommodate these
constraints.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88179
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A compaq_8300_elite_sff build can run on these models mostly unmodified.
Spawn a new variant from it, tie up some obvious loose ends and bring it
officially into the fold.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Ic0f04d586a8361968d7f6c3e3d048f945528cb84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
In order to support runtime evaluation of the TPM base address
introduce and use a new method for CRB TPMs.
Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Add support for the Memsic MXC6655 accelerometer on I2C0, as an
alternative to the existing Kionix KCXJ9. Use the "detect" function
of the I2C generic driver to determine which is present at runtime.
TEST=build/boot starlite_adl with MXC6655, verify screen roation works
properly when detached from keyboard under Linux and Windows.
Change-Id: I59d424903cceda9871855372e1d666eaa12443b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Load PI image through CBFS and pass parameters of PI image to mtk_fsp
for parsing.
BUG=b:379008996
BRANCH=none
TEST=check the boot log:
[INFO ] CBFS: Found 'pi_img.img' @0x3d880 size 0x10b in mcache @0xfffdd314
[DEBUG] mtk_init_mcu: Loaded (and reset) pi_img.img in 14 msecs (720 bytes)
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Iada90ad4298d0a91ad73798252db19b12f2f6ef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88266
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To promote code reuse and maintainability, move PI image related code to
common folder. The function add_pi_image_params is renamed to
pi_image_add_mtk_fsp_params for prefix consistency.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If5e3d9e6d5f97ead763ef9adc2d23bce0ed68877
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88265
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The QCOM X1P42100 SoC requires images loaded by PBL in MBN v7
format. This script is updated to support MBN v7 format which will
be used to generate the Bootblock binary.
Starting with the Qualcomm x1p42100 SoC, the bootblock ELF header
expects MBN version 7 instead of version 6 with the SC7280 SoC. This
patch adds the necessary adjustment to ensure compatibility with older
SoC platforms and also adds incremental support for newer SoC
generations. If Qualcomm SoCs in the future demands a more advanced
version of MBN (version > 7), additional logic will be added to the
newly added section as `self.flash_parti_ver == 8`.
BUG=b:420542130, b:404985109
TEST=Create image.serial.bin with bootblock in MBN v7 format and
ensure it boots on X1P42100. Please refer to the steps mentioned
below to create final AP FW image for QC SoC X1P42100.
Step 1: Create Bootblock MBN image using createxbl.py script where the
newly added MBN v7 support will be used.
Step 2: Call create_multielf.py to create the concatenated multi ELF
( TME SEQ + TME FW + QC_SEC + BOOTBLOCK from step 1)
Step 3: Call nqgpt.py to create final GPT image.
Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88240
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refines the ROM size configuration for Google Bluey
mainboards by moving the `BOARD_ROMSIZE_KB_*` selection from the
common Kconfig to the specific board variants.
Previously, `BOARD_ROMSIZE_KB_65536` was selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This blanket setting is inaccurate as
different Bluey-based boards utilize different sized ROMs.
With this change:
- `BOARD_GOOGLE_BLUEY` now selects `BOARD_ROMSIZE_KB_65536`.
- `BOARD_GOOGLE_QUENBI` now selects `BOARD_ROMSIZE_KB_32768`.
This ensures that each board variant has the correct ROM size
configured, preventing potential issues related to image size or
flash programming.
TEST=Able to verify that google/bluey AP FW image os 64MB and
google/quenbi AP FW is 32MB in size.
Change-Id: Ifcf75b310f08cbc4bbbd27ad7947df06da4f5d5a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the SPI flash vendor selection for Google Bluey
boards to accurately reflect the components used by each variant.
Previously, `SPI_FLASH_WINBOND` was unconditionally selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This is incorrect as different Bluey
variants may use different SPI flash chips.
This change now specifically selects:
- `SPI_FLASH_MACRONIX` for `BOARD_GOOGLE_BLUEY`
- `SPI_FLASH_WINBOND` for `BOARD_GOOGLE_QUENBI`
This ensures that the correct SPI flash driver is enabled for each
specific board variant, as per underlying hardware design.
TEST=Able to build google/bluey.
Change-Id: I7deaed90a7f6533ed4fe9fd815715dabdaa561a3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit enables `ARM64_USE_ARM_TRUSTED_FIRMWARE` for the
Qualcomm X1P42100 SoC.
Selecting this option ensures that coreboot is configured to
integrate with ARM Trusted Firmware (TF-A), which is essential
for proper boot and power management functionality on this platform.
BUG=b:424149462
TEST=Able to build google/bluey.
Change-Id: I30bc3eb9eedcaaef67cccf8c2f29c6ed76c71e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
permanent_smi_handler and acpi_s3_resume_allowed returns boolean,
so use boolean instead of int.
Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
enable_power_saving is a boolean so use "true" "false".
Change-Id: I0f62fc2b0db3abd3f204951f15081b89e02a0754
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86608
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8189 is equipped with the Power Mode Resource Collector (PMRC)
feature, and the implementation to set PMIF to normal mode is the same
as in pmif_spmi_v2. Use pmif_spmi_v2 to correct the configuration to
allow PMIF to properly enter normal mode on MT8189.
BUG=b:379008996
BRANCH=none
TEST=check the following logs for PMIC communication
[DEBUG] pmic_efuse_setting: Set efuses in 10 msecs
[INFO ] [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ] [RTC]rtc_boot,330: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ] [RTC]rtc_enable_dcxo,66: con=0x486, osc32con=0xfe69, sec=0x0
[INFO ] [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
[INFO ] [RTC]rtc_osc_init,62: osc32con val = 0xfe69
[INFO ] [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88244
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
brox_rtk_ec share the same power design with brox,
so follow brox set as 9W.
BUG=b:414474440
TEST=system can boot when AC only.
Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
compiler-rt is not a variable used by the LLVM_ENABLE_PROJECTS config,
but has a separate configuration option.
Change-Id: Iacd9b5f1fc1444b3dd1a785b91510f346e7a2f51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80737
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old test code used outdated function declarations that break with
C23 in GCC 15. Instead of forcing C17 standard:
1. Add full prototype for g() function
2. Use 'void' for empty parameters
3. Clean up messy formatting
This keeps C23 compatibility while fixing the build.
Tested with GCC 15.1.0
The -std=gnu17 workaround is no longer needed.
Change-Id: I718a5ed5c11742b1c3448abf7198c96ac78bc98a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
"--parallel" is not a valid option for CMake.
Change-Id: Idba76ce6a29e5d582ce49aa91ce4013aebc6d835
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The mb/adlink directory no longer exists, so remove it from the list of
checked directories.
Add a check to make sure that the directory exists before trying to lint
it in the future.
Change-Id: I59874cb7356c2e8eeb8fc216f2930b3d8ef513c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88237
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Change .inc to .mk. This was missed when renaming the makefiles.
- Verify that dirs/files exist before checking.
- Use $FINDOPTS to control search when not in a git repo.
Change-Id: If0d80403a3e799b8103164cc075601a50c33a8d9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Kconfig linter was browsing into the openSIL tree and reporting
issues for the release because it can't use git grep there. This change
explicitly tells the Kconfig linter to ignore the openSIL submodule.
Change-Id: Ia0399225cced9f199a6d2a90bc6c2af905ff4e99
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The binary files were not being correctly filtered. This tells grep to
just ignore binary files. This isn't particularly important inside the
git tree, but for releases where we can't use git grep, it becomes an
issue.
Change-Id: I2852ea1e8b0f337aa5c78daa5e9dbd0c3d6768a9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Group the variables by toolchain (GCC vs Clang) and order them by
build sequence.
Change-Id: Ifd911b719882adf1d2e9211f6009b579f8177abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88227
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow baseboard nissa and project pujjocento project to setting
GPE configuration.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS.
Change-Id: I75deadd0c1b7218c2d0820d637cc2ec02bf9154f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MT62F2G32D4DS-023 WT:C in the memory_parts.json and re-generate the
SPD.
BUG=b:427327667
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I8f244c2f91d66ffcbc1ec2642304f77b522da09f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Replace `data.vbt` with version from Intel FSP repository to match
the updated FSP release used in this platform.
This change is required when using 3rdparty/fsp/AlderLakeFspBinPkg
commit: 15848ee4934acbd94069454f369e9869bb0f1295
which introduces the "IoT ADL-N IPU25.3 (6114_00)" release.
With the previous VBT, the system boots but fails to display
any graphics output (HDMI) during firmware POST and OS boot.
This updated VBT resolves the display initialization issue.
Source:
15848ee493/AlderLakeFspBinPkg/IoT/AlderLakeN/Vbt/Vbt_ADLN.bin
Change-Id: If948d3bbef02f516067db0bad07167bdf7c81ce2
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88191
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The addresses and their modes should now all be correct and we can
therefore treat the case where `addr` and `mode` do not match as an
actual error.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id12c29648c0437dd082b471689ec3649314dee1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There is no need to treat the APOB_NV binary special anymore, as
the mode and address should now always match for the APOB_NV address.
Since phoenix SOC generation this code even errors out on VBOOT
platforms, because APOB_NV address is actually a BIOS relative address.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I64d43e654e3694d7590edcba9a87c98367a7256c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In order to not change the actual binaries in too many ways,
commit a7eb390796 ("mb/*/*/*.fmd: Start flash at 0") kept the current
behaviour in which the address mode was set to ADDR_REL_BIOS, but the
address itself was actually a physical address. It has probably only
worked all these years, because PSP/ABL code did apparently ignore the
address mode for this specific binary for generations previous to
phoenix.
Assuming the address mode is actually ignored we might as well use the
right address mode corresponding to the address that is set. That way
tooling that is used to inspect this image is not completely confused.
This sets the ADDR_PHYSICAL address mode to all generations that have
the APOB NV quirk. It therefore only affects these generations (previous
to phoenix).
tested:
Check that the binary is identical on bilby, morphius, kahlee, onyx and
birman_plus. bilby, kahlee, onyx don't have an APOB_NV region. morphius
uses a physical address anyway and birman_plus doesn't have the
apob_nv_quirk.
Check that only the address mode is changed to ADDR_PHYSICAL (and the
checksum of the table) on guybrush, frostflow, crater, chausie.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib2edfb27ba0fa316f1fbe31bc0ad8e2060a70f48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87296
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the code to amdfwtool.c, because the subsequent patch needs
it to be there in order to properly update the address_mode.
This patch should not change the binary in ANY way on any platform.
tested: Check that the binary is identical on guybrush, birman_plus,
frostflow, bilby, crater, grunt, myst, onyx_poc, morphius
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9c64c67ff8b9656516344fdafbfd2254abfceeef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
