The address field of each PSP or BIOS entry defines the location of
the entry.
For the family newer than Cezanne, the upper 2 bits define the address
mode. In table header, the address mode of the table is set. They have
the same definition.
Address Mode 0: Physical Address
Address Mode 1: Relative Address to entire BIOS image
Address Mode 2: Relative Address to PSP/BIOS directory
Address Mode 3: Relative Address to slot N
In common case, the address mode of entry should be the same as its
table. In spec, it says, "attribute is ignored if the directory
address mode is not 2 or 3",
In the old code, if the header defines address mode as relative BIOS(1),
the entry address mode is not set. That meets the spec. PSP doesn't
use, but amdfwtool can use it to record the address mode and transfer
it to table. That can reduce the code complexity.
Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.
Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84530
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Move the VBIOS checksum code into the soc/amd folder, as it's
specific to AMD's FSP. The code now fixes the VBIOS in place
instead only fixing it for the VFCT table.
TEST: VBIOS has correct checksum after loading in BS_DEV_RESOURCES.
VBIOS checksum is invalid entering graphics_dev_init().
VBIOS checksum is correct leaving graphics_dev_init().
Change-Id: I63aaaefaf01ea456e2ed39cd0891e552a7fb5135
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86384
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Option ROM contains lots of 16bit values that are being used,
thus use the 16bit endianness conversion function over the 32bit
variant to avoid confusion.
TEST: Still works on amd/birman+.
Change-Id: I571be97a930ad018e1d1316117cefe5bd1c68f9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86383
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On glinda the IGD is no longer VGA compatible. It doesn't
advertise itself as a VGA compatible devices and doesn't decode
the legacy VGA ranges 0x3C0-0x3CF, 0x3D4.
Introduce a new Kconfig and select it where necessary to keep
existing behaviour on older SoC while fixing FSP GOP init on
glinda. The VBIOS will get loaded into the D-segment instead
the C-segment, which is typically used by VGA.
TEST: FSP GOP on amd/birman+ is able to find the VBIOS.
amdgpu driver still doesn't work as the VFCT table isn't
generated on amd/glinda.
Change-Id: I6ab28aab74f3169d45d7d852a37ddfcfc75b7c88
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86300
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement vbt_get() on AMD and return the VBIOS location. This allows
to drop the hardcoded addresses used in various places and return an
address in DRAM that is reserved for FSP use.
TEST: amd/birman+ still gets passed the correct VBIOS address.
Change-Id: I92d76fc4df88fbce792b9d7c912c6799617704a0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86299
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Set open-drain GPIOs for ChromeOS as input and bias-disable mode.
After applying this patch, the voltage of these pins will become the
expected value 1.8V (previously 1.0V), preventing wrong judgement of
low/high.
BUG=b:396106564
TEST=emerge-rauru coreboot
BRANCH=rauru
Change-Id: I76c7931a56540a395eaf934125bded7fede84992
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses
this pin to determine the AP power state. This pin should be set as
early as possible in bootblock.
BRANCH=rauru
TEST=Build pass, reboot pass, suspend/resume pass.
BUG=b:395737458
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86381
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Birman+ has a 64MiB flash chip.
Update the mainboards Kconfig comment and fix the FMD to generate a
64MiB ROM. Until now only the first 16MiB are being used.
TEST: Still boots on AMD/Birman+
Change-Id: I72e3dcb0c3a308c3b0fd981b56cc7c1ef60095cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86179
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the SMMSTORE region to the default FMAP to allow
building for EDK2 as payload.
TEST: Still boots on AMD/Birman+
Change-Id: I661fcc55bf30aa6f1f3cc8a57e6d0eaf2fed4621
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86177
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns.
Additionally, a hardware solution of SPMI damping to 0 ohm is needed.
BRANCH=rauru
TEST=Build passed and booted successfully. 10 platforms have passed CPU
stress tests over multiple iterations.
BUG=b:386438329
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Remove GPP_E13 from being used as RAM ID3.
Planned to be used as a strap pin to disable memory channels
for x32 memory configuration.
BUG=b:379311559
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86362
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements the `google_chromeec_do_early_poweroff`
function for the Chrome EC. This allows the system to power
off before memory initialization by triggering an EC reset
with EC_REBOOT_COLD_AP_OFF.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: Ia53469feb2a020b38a5414728159b09c86c7e32d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86337
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit replaces the hardcoded 25 values for CPU TDP with the
TDP_25W macro.
Change-Id: I45cf507fe5300466519aafb0b920c8ae1d62ace0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Configure PMIC register 0x50c bit0 which decides whether to use external
xtal. This bit of mt6685 should be set to 1, to disable external xtal.
BRANCH=rauru
BUG=b:395485005
TEST=emerge-rauru coreboot chromeos-bootimage, remove battery and
charger, then insert battery and charge, RTC boots normally.
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Change-Id: Iea44f13af030f24c02993dd43a35a9d8b4f72179
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86353
Reviewed-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The tvdpll3 cannot be disabled during suspend because of the enable
operation, so we remove the enable operation. Hardware can now
automatically enable and disable tvdpll3 based on the clock demand of
its downstream.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86343
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
As MT8196 won't be able to boot up without mtk_fsp_romstage.elf and
mtk_fsp_ramstage.elf, ensure their presence in build time.
Change-Id: I668319ae1f63818e324002e7ae4d888479edb9cf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
selfboot() doesn't really need to be architecture dependent. All
architectures are essentially doing the same thing with a normal
function call, only x86_32 needs an extra attribute. arm64 and x86 also
previously haven't been passing the coreboot table pointer, even though
they should. This patch fixes that.
Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86142
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial override devicetree for dirks based on the
latest schematic (0W4_TWL_A_MB_0120.pdf).
- Add eMMC DLL tuning value (copy from riven)
- Configure I2C buses
- Configure USB ports
- Configure audio codec
- Configure WIFI6(CNVi) and WIFI7(PCIe)
Note :
There will be a separate CL to configure the implementation of
repurposing the TCSS port to USB Type-A after FSP support is added.
BUG=b:389391653
TEST=none.
Change-Id: Ic0b80e3121d94ede771ecc30cf0c66a67b9a41d0
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86250
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Correct MMinfra vote register to fix MMinfra power off failure during
suspend.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch,
mminfra can be turned off to reduce power consumption by 50mW.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86342
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to a maximum value of 16mA. Additionally, a hardware solution of
external pull-down is also required.
BRANCH=rauru
TEST=Build passed and booted successfully. The platform remained idle
for approximately 20 hours without hang.
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The code flow isn't that obvious in the beginning. You pass an address
of the VBIOS to FSP, but don't load any VBIOS until BS_DEV_RESOURCES
phase.
Add comments to document what is done and when. This will help to
improve the code in the next step.
Change-Id: I643bc9088306d99cc0fbb79648809e16b068fb33
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move all of the EC-related CFR options into a header in the ec
directory, so it can be reused across multiple boards.
TEST=build/boot starlabs/starbook_mtl,starlite_adl and verify CFR
options work properly.
Change-Id: I831559184de917b32e4993e8e34ffbc7b7e883e4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86318
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the POST brightness level in the VBT from 50 to 150 (max 255).
Change-Id: I1704a3479c38510b29427d582ee14c740401cd38
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86345
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Desktop devices don't need and shouldn't define a lid switch.
TEST=build/boot starlabs/byte,starlite_adl
Change-Id: Iecf3e2558e244cc0bec301a505c0bc86684954aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Commit `57aca97a2c` correctly changed the
reset types of GPIOs used in ACPI, but incorrectly set the pads to GPIO
mode, rather than ACPI mode.
This patch corrects that.
Change-Id: I7207d4d00e810c15d071eca0bea83796989e3735
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are not connected, so configure them as such.
Change-Id: I5dfeb5c1503ca85baf3641f1f5803519ec517b81
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit adds power limit configurations for additional variants of
the Intel PTL-H platform found on Fatcat. Specifically, it adds entries
for PCI Device IDs 2, 3, and 4. These configurations define the PL1,
PL2, and PL4 power limits, as well as the associated CPU TDP and
power limits index. The PL4 values are currently placeholders and
marked for future fine-tuning.
BUG=b:395130929
TEST=Able to boot google/fatcat with 65W USB-C PD charger.
Change-Id: I86befb07f39a5e292365ea40ea08d0f93f38a7a6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86339
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
The configuration used was copied from other boards in the tree,
NF1/NF2. However, no Intel documents says that GPP_E8 has a native
function.
As it remains unclear if the other boards in the tree are
misconfiugured, or the documents are incorrect, revert to a safe
configuration for the GPIO.
Change-Id: I49b8faa7f8712ad0ead22b7ccbfa6deca6046368
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `.devices` line only had once space before the =, as the tab
boundary is directly after the s of devices. The lines above had once
space after the last tab, so the equal sign is closer to the left side.
As the whole file aligns the equal sign, replace the space by a tab, and
do *not* go the route of not aligning the equal signs.
Change-Id: Ic49dc56263cafce3cfe40bb3ed7036fa25300f9f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit adds a new event type, `ELOG_TYPE_LOW_BATTERY_INDICATOR`,
to the event log. This event is logged when the system boots due to
a low battery condition. It includes the reason for the shutdown,
currently only supporting "Power Off".
BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.
```
> elogtool list
9 | 2025-02-03 09:44:19+0530 | Low Battery Boot | Power Off
```
Change-Id: I5cc5e5f540657c7dfd174a4928e697a272da813a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch disables eSOL Kconfig until the feature is ready in PTL
FSP-uGOP binary.
TEST=Able to build and boot google/fatcat to OS.
Change-Id: I99dd516816995b6cdfdcec618c06c7dbe061718a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86314
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Modify the I2C frequency of the touchpad to below 400 KHz to
meet the spec.
2. Modify the Thd dat of DATA between 0.3 us and 0.9 us to meet
the spec.
Before:
I2C5 - 407KHz
Thd - 0.06us
After:
I2C5 - 387Khz
Thd - 0.34us
BUG=b:391796230,b:391788680
TEST=Check that the wave form meets the spec.
Change-Id: I3c8c8d3b78236247ca7be810ac152085f615a6ef
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86324
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
With 8254 timer enabled, system would hang while entering s0ix state.
If we build coreboot with both timers =N, system enters s0ix state
(although it doesn't cut the power to the platform) and can be woken
up by pressing the key on the keyboard.
Since there's less potential for data loss in case of accidental
suspend, I think it makes sense to do it this way.
Change-Id: If6e0ac1d289447c292a49111251d321c951078e2
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TCSS_XHCI controller has a single USB2 port followed by 4 USB3
ports; the XHCI controller has 12 USB2 ports followed by 2 USB3
ports. The topology was queried from the root hub on each controller
and returned via the descriptor.
Add the 2 missing USB2 ports to the XHCI controller and the one to
the TSS_XHCI controller.
TEST=build/boot Win11, Linux 6.x on starlabs/starbook_mtl.
Change-Id: I5dc97f150ff064d55e7969f10c1cea8ba72d6bfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Measure mtk_fsp_load_and_run() execution time. This info helps AP boot
time analysis. The logs show as below.
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase 0x30 in 0 msecs
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 in 41 msecs
BUG=none
BRANCH=rauru
TEST=cbmem -1|grep "mtk_fsp_load_and_run"
Change-Id: I61706952bef4590c5bfd09707a08a4f1a25fbda2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Fix USB port assignments/descriptions to match actual topology.
TEST=build/boot Win11 on starlabs/starbook_mtl. Verify ports
match assignmented in devicetree using USBTreeview.
Change-Id: Ifb5ac4cf95c8f10706404479dea48ba20a90e286
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Including the Virtual Button Driver made laptops report as a detachable
in tablet mode. Adjust how it's included, so they report as laptops.
Change-Id: Idc2076c400524744836e2f52124ccb8502622b04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the board type to ULX as seen in the AMI CRB. This fixes
failed memory training for certain memory modules.
Change-Id: I951387fcfc0be8fb931b4c5ac0b5f022e057b371
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are not referenced anywhere, so remove them.
Change-Id: Ieb66099dcb9e13b26e6a7a752584537c060c8c18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86317
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorder the PCIe reset before mtk_dram_init to overlap the de-assert
time with the DRAM initialization process. This change helps to optimize
the initialization sequence and reduce overall boot time.
BRANCH=rauru
TEST=Build pass
BUG=b:391333055
Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit sets the TCC offset for the Fatcat baseboard variant.
A value of 10 was chosen, resulting in a TCC trip point of 100C
(Tjmax of 110C - offset of 10C).
This allows for thermal throttling to begin at a more appropriate
temperature.
Fatcat variants can override the TCC offset as per platform
requirements between power and/or performance.
TEST=Able to build and boot to CrOS.
Change-Id: I2a57fd3b06378f4e62872ffeb116a65561100e33
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86292
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
