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mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3

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Remove GPP_E13 from being used as RAM ID3.
Planned to be used as a strap pin to disable memory channels
for x32 memory configuration.

BUG=b:379311559
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86362
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Su 2025-02-11 17:53:20 +08:00 • committed by Subrata Banik
commit a89c4624bd
2 changed files with 3 additions and 5 deletions
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4
src/mainboard/google/brya/variants/uldrenite/gpio.c
View file

@ -184,8 +184,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
/* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */
PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
/* E13 : NC ==> RAM_ID3 */
PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E13 : NC */
PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : NC */

4
src/mainboard/google/brya/variants/uldrenite/memory.c
View file

@ -81,13 +81,11 @@ int variant_memory_sku(void)
* GPIO_MEM_CONFIG_0 GPP_E2
* GPIO_MEM_CONFIG_1 GPP_E1
* GPIO_MEM_CONFIG_2 GPP_E12
* GPIO_MEM_CONFIG_3 GPP_E13
*/
gpio_t spd_gpios[] = {
GPP_E2,
GPP_E1,
GPP_E12,
GPP_E13
GPP_E12
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));