erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/trulo/var/uldrenite: Support x32 memory configuration

Browse source 
Use the GPP_E13 level to determine whether x32 memory configuration
is supported.

BUG=b:379311559
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86364
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
John Su 2025-02-11 18:13:30 +08:00 • committed by Subrata Banik
commit b6c02d660c
3 changed files with 19 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/mainboard/google/brya/Kconfig
View file

@ -644,6 +644,7 @@ config BOARD_GOOGLE_ULDRENITE
select HAVE_WWAN_POWER_SEQUENCE
select DRIVERS_WWAN_FM350GL
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select ENFORCE_MEM_CHANNEL_DISABLE
config BOARD_GOOGLE_VELL
select BOARD_GOOGLE_BASEBOARD_BRYA

6
src/mainboard/google/brya/variants/uldrenite/gpio.c
View file

@ -184,8 +184,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
/* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */
PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
/* E13 : NC */
PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E13 : NC ==> GPP_E13_STRAP */
PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : NC */
@ -418,6 +418,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
/* E3 : PROC_GP0 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
/* E13 : NC ==> GPP_E13_STRAP */
PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* F12 : NC ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 0, DEEP),
/* F13 : NC ==> PLTRST_WWAN# */

14
src/mainboard/google/brya/variants/uldrenite/memory.c
View file

@ -3,6 +3,7 @@
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/romstage.h>
#include <soc/meminit.h>
static const struct mb_cfg variant_memcfg = {
.type = MEM_TYPE_LP5X,
@ -109,3 +110,16 @@ void variant_get_spd_info(struct mem_spd *spd_info)
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
spd_info->cbfs_index = variant_memory_sku();
}
uint8_t mb_get_channel_disable_mask(void)
{
/*
* GPP_E13 High -> One RAM Chip
* GPP_E13 Low -> Two RAM Chip
*/
if (gpio_get(GPP_E13)) {
/* Disable all other channels except first two on each controller */
return (BIT(2) | BIT(3));
}
return 0;
}