This GPIO isn't conencted, so configure it accordingly.
Change-Id: I2b027a1181de67e9a33bbb2062573c071827134a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Meteor Lake doesn't seem to configure the eSPI GPIOs for S3 on
reset, so add configuration from them so coreboot can configure
them correctly.
Change-Id: I4b74d320977faa60441e3d8b12980ef6ec41549d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87008
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The comment was reversed for the eSPI strap, so the GPIO was
misconfigured. Correct the comment and config accordingly.
Change-Id: I494d247ea4625fa1633ffa6d073b48f1dbf8432f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
config->cnvi_wifi_core and config->cnvi_bt_core are false by
default. This commit suppresses the acpi/acpigen.h inclusion, which is
unnecessary as well.
Change-Id: I2e171d6388b472f4cb877fdd93771142f9a3f2de
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Other types of FWs in the BIOS table are defined by context. So the
BIOS binary should follow that.
TEST=Binary identical test on platforms before mendocino
Tested on Skyrim
Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85466
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Process the single SPD data file which resides in cbfs. Add Kconfig
switch for SPD data in cbfs and include Nanya_NT6AP512T32BV-J1I.spd.hex
into the build by adding a correspondig Makefile.mk in the spd folder.
Additionally to load the memory configuration FSP-M parameters for the
romstage are set.
Loading SPD data from HWILIB was the technique applied by mainboard
siemens/mc_ehl2 from which this mainboard was copied. On fa_ehl
SPD data is stored in CBFS and gets loaded from there.
Change-Id: If84373dfbc1ecbf916489af6e964f8a7541f5e7b
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
It is more reasonable. And, in later change, the Level 1 should be
split with Level 2 and combined with EFS.
Change locate_bdt2_bios to locate_bdt_bios. This function is more
flexibile and covers both L1 and L2 BIOS directory table.
Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84532
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is now drawn (indirectly) from main usb_port_config.
Also drop it from autoport.
Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85925
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As of commit a3d1e6c480 ("sb/intel/bd82x6x: Apply EHCI mapping to
xhci_overcurrent_mapping"), this is now linked to main USB port config
and is no longer referenced separately.
This board is the last unresolved mismatching xhci_overcurrent_mapping
and there is no reports whether it is working or broken. Since the
value is no longer used anyway, remove it and put a FIXME in its place.
Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This board has an effectively broken USB configuration, which made
itself known during testing on a Pro 6300 SFF, that could run an
unmodified build for this variant and actually share the same vendor
BIOS update file (sp95971 v3.08 rev A).
Further examination of the BIOS update reveals five possible sets
of USB port configurations for all models covered by that update,
selected by PCH GPIOs 38 & 49, none of which matches what was currently
coded.
Then I received the autoport log from hardware with vendor BIOS that
confirmed my theory. Therefore apply the USB port config found therein.
While I'm at it, remove xhci_overcurrent_mapping, made obsolete by
commit a3d1e6c480 (sb/intel/bd82x6x: Apply EHCI mapping to
xhci_overcurrent_mapping).
Change-Id: Idc469b1aedcad2978247b9f6efbc7f55964e9ed1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement logo bitmap rotation within fsp_convert_bmp_to_gop_blt() to
support devices with portrait-oriented displays. The rotation is driven
by the panel framebuffer orientation, allowing the logo to be displayed
correctly regardless of physical panel orientation.
This resolves issues where the logo was displayed incorrectly on
portrait-oriented displays.
Additionally, discard the display orientation change if the LID is
closed aka built-in display is not active. This will ensure that
display orientation is proper when extended display is attached w/o
any display rotation.
BUG=b:396580135
TEST=Verified BMP logo display in landscape mode on a portrait panel
with rotation enabled. Also verified portrait logo display in landscape
mode with rotation enabled.
Change-Id: I110bd67331f01e523c227e1a4bdb0484f0157a60
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86850
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FW_CONFIG_SOURCE_CBFS option serves as a backup for
FW_CONFIG_SOURCE_CHROMEEC_CBI, utilizing variables stored in CBFS.
When using ChromeEC CBI as the firmware configuration source,
changes to fw_config values can be made without updating the firmware
image. However, using CBFS as the configuration source requires
resigning the firmware because the current implementation reads from
the RW firmware region (FW_MAIN_A/B), necessitating resigning for
updates. To avoid this step, the code should be modified to use the
RO CBFS for fw_config values instead of the RW (Read-Write) CBFS.
TEST:
1. Add FW_CONFIG_SOURCE_CBFS in board Kconfig and build image
2. Modify fw_config value by cbfstool with built image
3. flash and boot up system
4. Check updated fw_config value
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4710a1043fe75888d2dcaee98c6957e6bd639be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86943
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Update device tree to support Focal touchpad.
BUG=b:404363997
TEST=emerge-fatcat coreboot and Focal touchpad can work well.
Change-Id: I515eb63a9e5b8e4ebc7d6828ae3da47caa997ea3
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86979
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apply the change made to brya/redrix in CB:86749 to all applicable brox
variants, which is currently jubilant only.
BUG=b:397355818
TEST=Dump SSDT on jubilant
Change-Id: Ie0fc00e511b8efd5bae29cc089a24f7b0128d77e
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86954
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pad isn't used, so set it to not connected.
Change-Id: Ic7174457f56e64751718dc10227ec07b793559eb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86988
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit configures the GPIO_SLP_S0_GATE pin for the francka and
felino mainboards, which are used to gate the SoC's SLP_S0# signal
for proper sleep state management.
- For francka, GPIO_SLP_S0_GATE is set to GPP_F23.
- For felino, GPIO_SLP_S0_GATE is set to GPP_D03.
The base fatcat board and its variants (fatcatnuvo, fatcatite,
fatcatish) do not utilize this pin, therefore it is defined as 0
(Not Connected).
Change-Id: I3150d4e60e4886fb7df7229eaf9efed59a69a707
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86984
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
The fatcat variant now handles SLP_S0 pin functionality natively,
removing the need for HAVE_SLP_S0_GATE. However, other variants like
felino and francka boards still rely on this Kconfig option for proper
sleep state gating. This commit re-enables it for these specific boards.
TEST=Able to build and boot google/fatcat.
Change-Id: Ib7e683c3fee575245e8796638260f1fd8e6e5c34
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86983
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables EC software sync specifically for the Microchip EC
on the fatcat/fatcat-ish board. This change selects
`GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC` for boards w/ microchip EC
(EC_GOOGLE_CHROMEEC_MEC) like fatcat and fatcat-ish.
This allows other fatcat variants (Nuvoton, ITE EC AIC) to potentially
enable EC software sync, which is not compatible with the Microchip EC.
BUG=b:368278795
TEST=Verified EC software sync functionality on a Nuvoton AIC fatcat
variant.
Change-Id: I33c82c05a810c0328de5513f452505f2d560cf91
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86982
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Select FSP Type IOT so that the FSP blobs from the Intel repo are
used, as the client ones are not available.
Change-Id: Iefe8abc9741f9a77b7d55168a0ac42bf607fdb7c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
mtrr_use_temp_range() is used to temporarily cache the area(s) of RAM
to which the SPI flash is mapped, in order to speed up reading the
payload out of flash in preparation for execution. On systems with more
than 32GiB of RAM, there are not enough MTRRs available to map the
"permanent" regions below 4GiB, these temporary regions below 4GiB, and
any RAM above 4GiB due to fragmentation in the various ranges, as well
as limitations on the area covered by a single MTRR due to how they
are stored in the CPU registers.
As a workaround, if the number of MTRRs needed for the temporary map
exceeds the maximum available for the system, retry calc_var-mtrrs()
with `above4gb` set to false.
TEST=build/boot starlabs/starbook_mtl with > 32GB RAM, verify temporary
MTRRs are able to be assigned via cbmem console log, and no boot delays
in payload loading/decompression due to the SPI flash not being cached.
Change-Id: Ia9f9a1537e7e0c2f7ce21067eceb1549d0f9ea5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Cleans up a nit identified by Martin when adding a very similar
variant.
Change-Id: Id19054c08643cf03b2afbfe4c8929ce9dacaea5c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Since CNVI BT Offload is not yet ready on Pantherlake and HW already
soldered these 4 pads connection onto the board, therefore keep
Pad Config NC_LOCK and BT offload disable.
BUG=b:397578690
Test=emerge-fatcat coreboot and make sure WIFI/BT works
Change-Id: I2d84e8cff499d462133143b12fa6335e76323926
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86944
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This reverts commit 2da8d8affc.
Reason: The ISH firmware is renamed to trulo_ish.bin in the rootfs
itself hence this change is not required.
BUG=b:401138236
TEST=S0ix on Trulo and Truloti.
Change-Id: Ic21c9e2a28113dbd58ac992a380df601d058b16c
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86976
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables the crossystem utility to access WP GPIO.
TEST= wpsw_cur in crossystem reads the correct gpio
Change-Id: Iedf4d73a85e4159b4236e13d6aa8ff5e6fe2fcb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Use the ISH firmware file name as in rootfs.
BUG=b:401138236
TEST=suspend_stress_test is successful.
Change-Id: I29fbb4d9f04c23c1499dff5ffeab93e70675ae51
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
calc_var_mtrrs() calculates the number of MTRRs needed for both WB and
UC default memory types, and returns the type that uses fewer MTRRs.
Modify it to return the number of MTRRs used as well, and if that
count exceeeds the number available on the system, throw an error
and skip calling prepare_var_mtrrs() as we know it will fail.
TEST=tested with rest of patch train
Change-Id: I2be7c5b3385731f4dc9ef62de15dcf6d4cceb5d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86955
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No need for this to be a signed or unsigned int.
TEST=tested with rest of patch train.
Change-Id: I409c04b928211e0e89eec324fdf3fa3997c73576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86942
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable SD function based on SCH_MB_V3_A
RTD3 configured by HW design,PERST# and WAKE# pin connected to PCH
PLT_RST_N and Wake_PCH_N.
BUG=b:404409600
TEST=Boot OS from SD card and card detected works on OS
Change-Id: Ib7cb09edc3f07559f0013a3c554c97349e60f117
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86945
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the circuit schematic diagram, FPR feature need add
SLP_S0_GATE_R with or gate to control. Use gpp_a7 as SLP_S0_GATE_R
and add a variant specific S0ix hook to fill the SSDT table to control
FPR feature during suspend and resume respectively.
BUG=b:402629294
TEST=emerge-nissa coreboot. Test by EE, GPP_A7 pull down when do suspend
and pull high when resume.
Change-Id: I2334ef1e91776b292639f56b931f650f0661a69d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add display panel info and ACPI includes to enable display backlight
control under Windows and MacOS.
TEST=build/boot Win11 on sarien, verify brightness controls functional.
Change-Id: Ic0595c8c977f1203424ab9d91343b8e98414f594
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86907
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Arcada and Sarien use different VBTs in the current stock ChromeOS
firmware, so use the correct VBT for each. Files taken from images
Google_Sarien.12200.222.0.bin and Google_Arcada.12200.103.0.bin.
Change-Id: I0b07fadd34f84889c8bb186a9a22ed1bce36d6b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Taken from an ACPI dump from a Windows JSL device with MIPI camera.
Change-Id: Ibdb2b148ebfa85c3d4f5af2594b9b8847215e726
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/volteer (drobit), verify FPR does not
show up as unknown device under Device Manager.
Change-Id: I4b5962638128c73e1e752cf8c5f40e12deb9d96c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Enable the GNA PCI device, and include the ACPI stub so the OS driver
can attach.
TEST=build/boot Win10 on google/dedede (magpie)
Change-Id: I928bfe710e69bb43f177e3ce0c0077638233d44d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77579
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are used to control the rails, so enable them.
Change-Id: I3607dad4e57b99048aa7669c826fed046554333a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Determine CPU frequency & voltage for use in smbios type 4 table.
Reference:
AMD PPR 57254 v1.59 Section 2.1.15 CPUID Instruction
TEST=Build for glinda SoC & verify output to reflect CPU frequency
& voltage.
Sample Output:
dmidecode -t
...
Voltage: 1.2 V
...
Current Speed: 2600 MHz
...
Change-Id: Ibd7c7f1e299a0a8d294e7e30ae3130faae16ae22
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86757
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the generic x86 SPI flash mmap driver is being used when not
using DMA and when not on GENOA. It only works for ROM_SIZE of 16 MiB
or less and prevents boot when the ROM is bigger than that.
Use the genoa_poc SPI MMAP driver on all platforms by default as it
allows to use a ROM_SIZE greater than 16MiB. The newly introduced
Kconfig SOC_AMD_COMMON_BLOCK_SPI_MMAP is used for all platforms when
the SPI DMA driver is not in use.
This doesn't allow to access the whole SPI flash using the ROM2 MMIO
window, but it no longer prevents boot when the mainboard specifies
the correct SPI flash size in Kconfig.
TEST: Booted an AMD/birman+ with 64MiB ROM specified in Kconfig.
TEST: Booted on AMD/onyx with 32MiB ROM specified in Kconfig.
Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86618
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to return the position and size of the ROM2 and ROM3
MMIO windows that mmap the SPI flash. Starting from AMD Family 17h
Model 30h (Zen 2) the ROM3 BAR is available.
ROM3 is not supported on picasso or stoneyridge.
Document ID: 56780
TEST: Verified that both functions return sane values.
Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the LPC PCI device to make sure common code builds.
Document ID: 55898
Change-Id: I52b129b47f98d88cad1d656dab4d4562c7ce3394
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86706
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds initial dq mapping and spd data for LP5 memory
parts for GCS board. This also configures memory based on the board id.
Memory - LPDDR5x
Vendor/Model - H58G66BK8BX067
BUG=b:398880064
TEST=Boot to OS on GCS board.
Change-Id: I268ddf2d4b6361d9dabb217c4246cb6cc0e2144c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Commit 3ff85e5dcd ("soc/intel/alderlake:
Make Energy Efficient Turbo configurable") made the EnergyEfficientTurbo
User Product Data (UPD) adjustable, but it did not update the comment.
Change-Id: I34b8829efcfa3210950051e9b6d4d5a3c289ec93
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces the missing Fast Voltage Mode settings for the
Voltage Regulator (VR) applicable to the Intel Panther Lake (PTL)-U 15W
System on Chip (SoC) on the Google Fatcat mainboard. The configurations
have been populated in accordance with the specifications outlined in
Intel's Panther Lake Power Map document (reference number 813278). These
settings leverage the Fast Voltage Mode capabilities of the CPU cores
(IA), Graphics (GT), and System Agent (SA).
The voltage regulator settings are for PTL-U; therefore, when the
coreboot image is used on a Panther Lake H SKU, some lower performance
could be observed due to the I_TRIP value being lower than what the
device could actually use.
BUG=b:357011633
TEST=As no Panther Lake-U (PTL-U) SKUs were available, smoke tests have
been performed on Panther Lake-H (PTL-H). We verified that the
Firmware Support Package (FSP) successfully submitted requests to
the pcode firmware and that once the operating system was running,
S0iX entry and exit were operational.
Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Micron SPD file was removed and Nanya-NT6AP512T32BV-J1I.spd was added
as it will be used for the final product.
Change-Id: Icbfb3a51fcb7c09bad9b70861fa58f5c957ce1ae
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86423
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
