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mb/google/fatcat/var/felino: Enable SD Function

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Enable SD function based on SCH_MB_V3_A
RTD3 configured by HW design,PERST# and WAKE# pin connected to PCH
PLT_RST_N and Wake_PCH_N.

BUG=b:404409600
TEST=Boot OS from SD card and card detected works on OS

Change-Id: Ib7cb09edc3f07559f0013a3c554c97349e60f117
Signed-off-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86945
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dolan Liu 2025-03-21 10:55:06 +08:00 • committed by Matt DeVillier
commit c8069bc53f
1 changed files with 7 additions and 10 deletions
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17
src/mainboard/google/fatcat/variants/felino/overridetree.cb
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@ -197,17 +197,14 @@ device ref tbt_pcie_rp0 on end
end
end
device ref pcie_rp1 on
# Enable PCH PCIE x1 slot using CLK 2
register "pcie_rp[PCIE_RP(3)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
device ref pcie_rp2 on
# Enable PCH PCIE x1 slot using CLK 6
register "pcie_rp[PCIE_RP(2)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1,
}"
chip soc/intel/common/block/pcie/rtd3
register "srcclk_pin" = "2"
device generic 0 on end
end
end # SD Card
device ref pcie_rp4 on