mb/prodrive/atlas: Add initial support for options
The plan is to have a setup menu in edk2 to configure coreboot options without having to describe the options in both coreboot and edk2; that would be a maintenance nightmare. Options are passed to edk2 using CFR structures, edk2 stores the values in the variable store in flash, and coreboot reads the option values using the EFI variable store backend. Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
This commit is contained in:
Angel Pons
Lean Sheng Tan
parent
1a16146795
commit
97923aebe1
6 changed files with 287 additions and 10 deletions
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@ -13,6 +13,7 @@ config BOARD_PRODRIVE_ATLAS_BASEBOARD
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select MEMORY_MAPPED_TPM
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select PCIEXP_SUPPORT_RESIZABLE_BARS
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select SOC_INTEL_ALDERLAKE_PCH_P
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select DRIVERS_OPTION_CFR_ENABLED
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config BOARD_PRODRIVE_ATLAS
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select BOARD_PRODRIVE_ATLAS_BASEBOARD
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@ -23,13 +24,6 @@ config ATLAS_ENABLE_SAGV
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bool "Enable SaGv"
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default n
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config ATLAS_ENABLE_IBECC
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bool "Enable IBECC"
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help
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Enables In Band Error Correction Code. It's only needed for endurance testing
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and therefore not always required.
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default n
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config D3COLD_SUPPORT
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default n
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@ -8,6 +8,7 @@ bootblock-y += early_gpio.c
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romstage-y += romstage_fsp_params.c
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ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
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ramstage-y += gpio.c
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ramstage-y += mainboard.c
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ramstage-y += ramstage_fsp_params.c
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264
src/mainboard/prodrive/atlas/cfr.c
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264
src/mainboard/prodrive/atlas/cfr.c
Normal file
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@ -0,0 +1,264 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boot/coreboot_tables.h>
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#include <commonlib/coreboot_tables.h>
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#include <drivers/option/cfr_frontend.h>
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#include <intelblocks/pmclib.h>
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#include <inttypes.h>
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#include <soc/pm.h>
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#include <stdio.h>
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#include <string.h>
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#include <types.h>
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#include "vpd.h"
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static void update_rt_perf(const struct sm_object *obj, struct sm_object *new)
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{
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const bool rt_perf = get_emi_eeprom_vpd()->profile == ATLAS_PROF_REALTIME_PERFORMANCE;
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if (!rt_perf)
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return;
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if (obj->kind == SM_OBJ_BOOL) {
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new->sm_bool.flags = CFR_OPTFLAG_SUPPRESS;
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new->sm_bool.default_value = false;
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} else if (obj->kind == SM_OBJ_ENUM) {
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new->sm_enum.flags = CFR_OPTFLAG_SUPPRESS;
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new->sm_enum.default_value = 0;
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}
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}
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static void update_bad_profile(const struct sm_object *obj, struct sm_object *new)
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{
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const bool pf_ok = get_emi_eeprom_vpd()->profile != 0;
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if (!pf_ok)
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return;
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new->sm_comment.flags |= CFR_OPTFLAG_SUPPRESS;
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}
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static void update_serial(const struct sm_object *obj, struct sm_object *new)
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{
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new->sm_varchar.default_value = get_emi_eeprom_vpd()->serial_number;
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}
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static void update_part_number(const struct sm_object *obj, struct sm_object *new)
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{
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new->sm_varchar.default_value = get_emi_eeprom_vpd()->part_number;
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}
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static void update_profile(const struct sm_object *obj, struct sm_object *new)
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{
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new->sm_number.default_value = get_emi_eeprom_vpd()->profile;
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}
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/* TODO: Suppress option if carrier board is known to not have a RTC battery */
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static const struct sm_enum_value pwr_after_g3_values[] = {
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{ "Power off (S5)", MAINBOARD_POWER_STATE_OFF },
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{ "Power on (S0)", MAINBOARD_POWER_STATE_ON },
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/* No support for previous/last power state */
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SM_ENUM_VALUE_END,
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};
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static const struct sm_object power_on_after_fail = SM_DECLARE_ENUM({
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.opt_name = "power_on_after_fail",
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.ui_name = "Restore AC Power Loss",
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.ui_helptext = "Specify what to do when power is re-applied "
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"after a power loss. This option has no effect "
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"on systems without a RTC battery.",
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.default_value = CONFIG_MAINBOARD_POWER_FAILURE_STATE,
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.values = pwr_after_g3_values,
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});
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static const struct sm_enum_value primary_display_values[] = {
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{ "Intel iGPU", 0 },
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{ "CPU PEG dGPU", 1 },
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{ "PCH PCIe dGPU", 2 },
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{ "Auto", 3 },
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SM_ENUM_VALUE_END,
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};
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static const struct sm_object primary_display = SM_DECLARE_ENUM({
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.opt_name = "primary_display",
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.ui_name = "Primary display device",
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.ui_helptext = "Specify which display device to use as primary.",
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.default_value = CONFIG(ONBOARD_VGA_IS_PRIMARY) ? 0 : 3,
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.values = primary_display_values,
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});
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static const struct sm_enum_value pkg_c_state_limit_values[] = {
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{ "C0/C1", 0 },
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{ "C2", 1 },
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{ "C3", 2 },
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{ "C6", 3 },
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{ "C7", 4 },
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{ "C7S", 5 },
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{ "C8", 6 },
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{ "C9", 7 },
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{ "C10", 8 },
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{ "Default", 254 },
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{ "Auto", 255 },
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SM_ENUM_VALUE_END,
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};
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static const struct sm_object turbo_mode = SM_DECLARE_BOOL({
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.opt_name = "turbo_mode",
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.ui_name = "Turbo Boost",
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/* No help text */
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.default_value = true,
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});
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static const struct sm_object vmx = SM_DECLARE_BOOL({
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.opt_name = "vmx",
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.ui_name = "Intel Virtualization Technology (VT-x)",
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/* No help text */
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.default_value = false,
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});
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static const struct sm_object vtd = SM_DECLARE_BOOL({
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.opt_name = "vtd",
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.ui_name = "Intel Virtualization Technology for Directed I/O (VT-d)",
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/* No help text */
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.default_value = false,
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});
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static const struct sm_object ibecc = SM_DECLARE_BOOL({
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.opt_name = "ibecc",
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.ui_name = "In-Band ECC",
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.ui_helptext = "Specify whether In-Band error checking and "
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"correction is to be enabled. Enabling this "
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"option will reduce the amount of available "
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"RAM because some memory is needed to store "
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"ECC codes.",
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.default_value = false,
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});
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static const struct sm_object serial_number = SM_DECLARE_VARCHAR({
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.flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE,
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.opt_name = "serial_number",
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.ui_name = "Serial Number",
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}, WITH_CALLBACK(update_serial));
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static const struct sm_object part_number = SM_DECLARE_VARCHAR({
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.flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE,
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.opt_name = "part_number",
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.ui_name = "Part Number",
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}, WITH_CALLBACK(update_part_number));
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static const struct sm_object bad_profile = SM_DECLARE_COMMENT({
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.flags = CFR_OPTFLAG_READONLY,
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.ui_name = "WARNING: Profile code is invalid",
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}, WITH_CALLBACK(update_bad_profile));
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static const struct sm_object profile = SM_DECLARE_NUMBER({
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.flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE,
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.opt_name = "profile",
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.ui_name = "Profile code",
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.ui_helptext = "The profile code obtained from the EEPROM",
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}, WITH_CALLBACK(update_profile));
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static const struct sm_object energy_eff_turbo = SM_DECLARE_BOOL({
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.flags = 0,
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.opt_name = "energy_eff_turbo",
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.ui_name = "Energy Efficient Turbo",
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/* No help text */
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.default_value = false,
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}, WITH_CALLBACK(update_rt_perf));
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static const struct sm_object pkg_c_state_limit = SM_DECLARE_ENUM({
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.flags = 0,
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.opt_name = "pkg_c_state_limit",
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.ui_name = "Package C-state limit",
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.ui_helptext = "", /* TODO: write something */
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.default_value = 255,
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.values = pkg_c_state_limit_values,
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}, WITH_CALLBACK(update_rt_perf));
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#define NUM_PCIE_SSC_SETTINGS 21
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static struct sm_enum_value pch_pm_pcie_pll_ssc_values[] = {
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[NUM_PCIE_SSC_SETTINGS] = { "Auto", 0xff },
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SM_ENUM_VALUE_END,
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};
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static void update_pll_ssc_values(const struct sm_object *obj, struct sm_object *new)
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{
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for (size_t i = 0; i < NUM_PCIE_SSC_SETTINGS; i++) {
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char buffer[16];
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snprintf(buffer, sizeof(buffer), "%u.%u%%", i / 10, i % 10);
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pch_pm_pcie_pll_ssc_values[i].ui_name = strdup(buffer);
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pch_pm_pcie_pll_ssc_values[i].value = i;
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}
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}
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static const struct sm_object pch_pcie_pll_ssc = SM_DECLARE_ENUM({
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.opt_name = "pch_pcie_pll_ssc",
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.ui_name = "PCH PCIe PLL Spread Spectrum Clocking",
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/* No help text */
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.default_value = 0xff,
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.values = pch_pm_pcie_pll_ssc_values,
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}, WITH_CALLBACK(update_pll_ssc_values));
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static const struct sm_object c_states = SM_DECLARE_BOOL({
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.flags = 0,
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.opt_name = "c_states",
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.ui_name = "CPU power states (C-states)",
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.ui_helptext = "Specify whether C-states are supported.",
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.default_value = true,
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}, WITH_CALLBACK(update_rt_perf));
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static const struct sm_object hyper_threading = SM_DECLARE_BOOL({
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.flags = 0,
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.opt_name = "hyper_threading",
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.ui_name = "Hyper-Threading Technology",
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/* No help text */
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.default_value = true,
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}, WITH_CALLBACK(update_rt_perf));
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static struct sm_obj_form cpu = {
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.ui_name = "CPU",
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.obj_list = (const struct sm_object *[]) {
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&c_states,
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&hyper_threading,
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&turbo_mode,
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&energy_eff_turbo,
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&vmx,
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&vtd,
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NULL
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},
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};
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static struct sm_obj_form main = {
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.ui_name = "Main",
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.obj_list = (const struct sm_object *[]) {
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&serial_number,
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&part_number,
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&bad_profile,
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&profile,
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&power_on_after_fail,
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&primary_display,
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&pkg_c_state_limit,
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&pch_pcie_pll_ssc,
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&ibecc,
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NULL
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},
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};
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static struct sm_obj_form *sm_root[] = {
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&main,
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&cpu,
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NULL
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};
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/*
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* TODO: Writing this by hand is extremely tedious. Introducing a DSL
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* (Domain-Specific Language) to describe options which is translated
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* into code at build time may be the way to go. Maybe expand SCONFIG
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* so that these can be devicetree options?
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*/
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void lb_board(struct lb_header *header)
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{
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char *current = (char *)lb_new_record(header);
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struct lb_cfr *cfr_root = (struct lb_cfr *)current;
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cfr_write_setup_menu(cfr_root, sm_root);
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}
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@ -52,9 +52,6 @@ chip soc/intel/alderlake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
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register "ibecc.enable" = "CONFIG(ATLAS_ENABLE_IBECC)"
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register "ibecc.mode" = "CONFIG(ATLAS_ENABLE_IBECC) ? IBECC_MODE_ALL : IBECC_MODE_NONE"
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register "sata_salp_support" = "1"
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register "sata_ports_enable" = "{
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <option.h>
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#include <soc/ramstage.h>
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#include "vpd.h"
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@ -37,5 +38,17 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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params->PmcV1p05PhyExtFetControlEn = 0;
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params->PmcV1p05IsExtFetControlEn = 0;
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break;
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default:
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if (get_uint_option("c_states", 1) == 0) {
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params->Cx = 0;
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params->C1e = 0;
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params->C1StateUnDemotion = 0;
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params->C1StateAutoDemotion = 0;
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}
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params->PkgCStateLimit = get_uint_option("pkg_c_state_limit", 255);
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params->PchPmPciePllSsc = get_uint_option("pch_pcie_pll_ssc", 255);
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params->EnergyEfficientTurbo = get_uint_option("energy_eff_turbo", 0);
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params->TurboMode = get_uint_option("turbo_mode", 1);
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break;
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}
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}
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <fsp/api.h>
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#include <option.h>
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#include <soc/romstage.h>
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#include <soc/meminit.h>
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@ -48,6 +49,13 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
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memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
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const unsigned int def_prim_display = CONFIG(ONBOARD_VGA_IS_PRIMARY) ? 0 : 3;
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mcfg->PrimaryDisplay = get_uint_option("primary_display", def_prim_display);
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mcfg->VmxEnable = get_uint_option("vmx", mcfg->VmxEnable);
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mcfg->VtdDisable = !get_uint_option("vtd", !mcfg->VtdDisable);
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mcfg->Ibecc = get_uint_option("ibecc", false);
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mcfg->IbeccOperationMode = mcfg->Ibecc ? 2 : 0;
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/* Apply profile-specific settings */
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switch (get_emi_eeprom_vpd()->profile) {
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case ATLAS_PROF_REALTIME_PERFORMANCE:
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