mb/google/fatcat: Limit Power Limit when battery is missing
Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case.
BUG=b:377798581
TEST=See power limit override log message when the battery is missing
on fatcat board
Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85146
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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3 changed files with 34 additions and 0 deletions
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@ -32,6 +32,7 @@ config BOARD_GOOGLE_FATCAT_COMMON
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select MAINBOARD_HAS_TPM2
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select MB_COMPRESS_RAMSTAGE_LZ4
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select PMC_IPC_ACPI_INTERFACE
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select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
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select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
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select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
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select SOC_INTEL_PANTHERLAKE_U_H
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@ -1,3 +1,4 @@
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## SPDX-License-Identifier: GPL-2.0-only
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romstage-y += memory.c
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ramstage-y += ramstage.c
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <ec/google/chromeec/ec.h>
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/*
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* SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
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* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
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*/
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const struct cpu_tdp_power_limits power_optimized_limits[] = {
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{
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.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
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.cpu_tdp = 25,
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.power_limits_index = PTL_H_1_CORE,
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.pl1_min_power = 10000,
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.pl1_max_power = 25000,
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.pl2_min_power = 50000,
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.pl2_max_power = 50000,
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.pl4_power = 50000 /* TODO: needs fine tuning */
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},
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};
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void baseboard_devtree_update(void)
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{
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/* Don't optimize the power limit if booting with barrel attached */
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if (google_chromeec_is_barrel_charger_present())
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return;
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if (!google_chromeec_is_battery_present())
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variant_update_cpu_power_limits(power_optimized_limits,
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ARRAY_SIZE(power_optimized_limits));
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}
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