drivers/amd/opensil: Add openSIL timepoint calls

Place openSIL timepoints 1, 2 and 3 calls in the driver, which will
serve as the central point for invoking SoC-specific vendorcode
implementations. TP1 and TP2 will initialize silicon pre- and post-PCIe
enumeration, respectively. TP3 then performs late SoC IPs programming
and register locking closer to payload load prior to OS handoff. Add a
Kconfig option for selecting and including the openSIL driver source
code in the build.

Change-Id: If0559fc0ff0ec55e9ef131e5ed20dfb5baa651da
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85631
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/amd/opensil/Kconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config OPENSIL_DRIVER
+	bool
+	help
+	  Indicate that the openSIL driver is being used on the platform.

src/drivers/amd/opensil/Makefile.mk

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_OPENSIL_DRIVER),y)
+
+ramstage-y += ramstage.c
+
+endif

src/drivers/amd/opensil/opensil.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef OPENSIL_DRIVER_H
+#define OPENSIL_DRIVER_H
+
+/* Set up openSIL env and call TP1 */
+void amd_opensil_silicon_init(void);
+
+#endif /* OPENSIL_DRIVER_H */

src/drivers/amd/opensil/ramstage.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <vendorcode/amd/opensil/opensil.h>
+
+#include "opensil.h"
+
+void amd_opensil_silicon_init(void)
+{
+	setup_opensil();
+	opensil_xSIM_timepoint_1();
+}
+
+static void call_opensil_xSIM_timepoint_2(void *arg)
+{
+	opensil_xSIM_timepoint_2();
+}
+
+static void call_opensil_xSIM_timepoint_3(void *arg)
+{
+	opensil_xSIM_timepoint_3();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, call_opensil_xSIM_timepoint_2, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, call_opensil_xSIM_timepoint_3, NULL);
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, call_opensil_xSIM_timepoint_3, NULL);

src/soc/amd/genoa_poc/Kconfig

@@ -48,6 +48,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_OPENSIL
 	select SOC_AMD_OPENSIL_GENOA_POC
+	select OPENSIL_DRIVER
 	select X86_CUSTOM_BOOTMEDIA
 
 config USE_X86_64_SUPPORT

src/soc/amd/genoa_poc/chip.c

@@ -3,16 +3,15 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
 #include <device/device.h>
+#include <drivers/amd/opensil/opensil.h>
 #include <soc/southbridge.h>
 #include <soc/southbridge.h>
-#include <vendorcode/amd/opensil/opensil.h>
 
 static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
 
-	setup_opensil();
-	opensil_xSIM_timepoint_1();
+	amd_opensil_silicon_init();
 
 	data_fabric_print_mmio_conf();
 

src/soc/amd/phoenix/Kconfig

@@ -104,6 +104,7 @@ config SOC_AMD_PHOENIX_OPENSIL
 	bool
 	select SOC_AMD_PHOENIX_BASE
 	select SOC_AMD_OPENSIL
+	select OPENSIL_DRIVER
 
 if SOC_AMD_PHOENIX_BASE
 

src/soc/amd/phoenix/chip.c

@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Phoenix */
-
 #include <acpi/acpigen_pci.h>
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
@@ -10,11 +8,12 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <drivers/amd/opensil/opensil.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <types.h>
-#include <vendorcode/amd/opensil/opensil.h>
+
 #include "chip.h"
 
 static const char *soc_acpi_name(const struct device *dev)
@@ -46,8 +45,7 @@ static void soc_init(void *chip_info)
 	if (CONFIG(PLATFORM_USES_FSP2_0)) {
 		amd_fsp_silicon_init();
 	} else {
-		setup_opensil();
-		opensil_xSIM_timepoint_1();
+		amd_opensil_silicon_init();
 	}
 
 	data_fabric_print_mmio_conf();