Introduce the MAINBOARD_HAS_PS8820_RETIMER Kconfig option. This will
be used to conditionally enable I2C initialization and retimer
configuration logic on Bluey variants.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Change-Id: I949fb16f8c46a8375b50d2b108b8edde3231f4e9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90710
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch implements the power-on and reset sequence for the USB-C1
retimer on the Bluey mainboard.
Sequence Details:
- romstage: Added early_setup_usb_typec to ensure all power rails
(3.3V, 1.8V, 0.9V) are disabled and the retimer is held in reset
early in the boot process.
- ramstage (mainboard): Added setup_usb_typec to perform the power-up
sequence with the required 1ms delays between rails to ensure
hardware stability:
BUG=b:473489095
TEST=Able to detect USB devices in HS mode.
Change-Id: Ia93c0078aecdec98f3af28e73e7af5af7a3b20d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Convert MIPI camera configurations from static ASL files to devicetree-
based runtime ACPI generation using the mipi_camera driver. This moves
the camera IPU and device definitions from static ASL includes to
devicetree overridetree files.
Changes:
- Convert baseboard, voema, volteer, and volteer2 from static
mipi_camera.asl files to devicetree configuration
- Move IPU0 configuration with CAM0 and CAM1 to volteer/volteer2
variant overridetree files (baseboard devicetree not used directly)
- Remove all static ASL camera definition files (mipi_camera.asl)
- Simplify voema variant to use only 1 IPU port (CAM1 only) instead
of 2 ports, removing unused CAM0 port definition
- Add SSDB config based on sensor name/type and CIO2 config
This, along with follow-on patches, will allow volteer variants to be
properly supported under Windows/Linux as well as ChromeOS.
Change-Id: I7bd4ef2812a3d21b6541469bc3a126498d72f5ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The previous implementation violated ACPI spec by attempting to
implement a reset via _ON/_OFF, which are to be used exclusively for
device power management/power state transitions. As a result, under
Windows the CNVi BT device was continually re-enumerating and unable
to be used.
Fix this by moving the reset logic out of _ON/_OFF and into _RST, where
it belongs.
TEST=build/boot Win11 on google/taeko, verify BT device is functional.
Change-Id: I1627fefbf7747129344291cc8855c15dda50cf5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90582
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Remove unused I2C3 pin configurations.
- Remove RST control. The ETU925 fingerprint module does not
need to control the RST pin.
BUG=b:452542491, b:467835297
TEST=emerge-ocelot coreboot
Change-Id: Ib4db733187d1b15f89654b53c1cf98420d652546
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90696
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
and USB-C1 Retimer I2C access
Load I2C firmware to QUPV3_0_SE3 and QUPV3_0_SE7 Serial Engines and
configure both in MIXED mode to enable I2C access for USB-C0 and USB-C1
retimers.
Test=
1. Created image.serial.bin and verified successful boot on X1P42100.
2. Read the corresponding QUP SE firmware revision read-only register
and confirmed that the protocol field (bits 8-15) matches the
programmed value. Register details are in HRD-X1P42100-S1
documentation:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Example:If programmed as I2C, the register value read is 0x00000303,
where 3 denotes the I2C protocol.
Change-Id: I337329628ac04246ab579e062a802a028cb4c560
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the battery state-of-charge print statement in romstage to
include a percentage symbol. This makes the log output more
readable and consistent with battery level reporting.
Use '%%' to correctly escape and print the literal '%' sign in
the printk statement.
BUG=None
TEST=Boot Bluey and verify romstage logs show "Battery
state-of-charge 95%" instead of "Battery state-of-charge 95".
Change-Id: I97b533567b56bfaba41508e35a6f324f0dbf331e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90684
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The KLED VBT file is misconfigured and results in an error under Linux:
[drm] ERROR VBT has malformed LFP data table pointers
Inspecting the VBT using the Intel BMP tool reveals invalid data for
many of the panel definitions, as well as other settings.
KLED works perfectly fine with the kindred VBT, so use that instead.
TEST=build/boot Win11/Linux on KLED, verify display output works
properly.
Change-Id: I09aaa5c17517633fdae508239ecf8e72e3990e33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
K3KL8L80CM-MGCT 4 (0100)
RS1G32LO5D2FDB-23BT 5 (0101)
BUG=b:472596025
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Iff12898dd6fb08a7e932de6e1902886a6f251761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add support to enable MMCX power rail and vote for MM0 BCM resource
required for display. This change includes support to enable display
clocks.
TEST= 1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump.
Serial Log:
[INFO ] RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ] ARC regulator initialized successfully
[DEBUG] RPMH_REG: Sent active request for mmcx.lvl
[INFO ] ARC level has been set successfully
[DEBUG] BCM: Found address 0x00050024 for resource MM0
[INFO ] BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ] BCM vote for MM0 sent successfully
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Change-Id: I89715fb4e3a6122388068a819e24cb409e204155
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90507
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Measured on Padme, the T3 (AVEE-to-RESET) timing in the current MIPI
panel power-on sequence is only ~120us, which is significantly shorter
than the panel specification requirement (>=3ms). This may cause panel
initialization instability due to RESET being asserted too early after
AVEE is enabled.
Increase the delay between AVEE enable and panel reset from 1ms to 5ms
to satisfy the panel T3 (AVEE-to-RESET) timing requirement.
IL79900A Power on off sequence V1.pdf
BUG=b:451746079
TEST=Boot Padme and confirm panel power-on timing is correct.
BRANCH=skywalker
Change-Id: Ided93c34f7c6695a2928c23eea679f32a0ee9a17
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Got this information from Bill Xie while troubleshooting CB:85413.
Apply the differences from vendor to coreboot.
Change-Id: I56f4314eca101cdfcac12594115d373472d1e1db
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the pair of non-ramstage Nuvoton SIO PNP config mode entry/exit
functions from early_serial.c into nuvoton.h as inline functions for
both pre-RAM and SMM code use. Availability is limited to
__SIMPLE_DEVICE__ environments, or if this symbol is defined such as
when mainboards specifically request it.
Cuts outdated comment from early_serial.c and transplant its key parts
to nuvoton.h.
Remove the temporarily refactored local copies from
mb/asrock/{z87_extreme4,fatal1ty_z87_professional}.
Build tested on these two Asrock boards and asus/p8x7x-series.
Change-Id: I0238f006dd86742f937e9dcd6134ed7be566677c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the pair of non-ramstage Nuvoton SIO config mode entry/exit functions
see wider use, they are being moved to sio/nuvoton/common.
This mainboard carries 2 local copies. This preparatory patch moves them
out of smihandler.c and mainboard.c into a temporary C file to prevent
build breakage. It is to be removed when the shared copy is in place.
WARNING: Disassembly of compiled SMM code shows a possible stack issue.
Do not flash a binary with this patch applied but without the final
shared version above.
Change-Id: I7a5394478281ac3b92d257e2f0201264b95bb4e5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the pair of non-ramstage Nuvoton SIO config mode entry/exit functions
see wider use, they are being moved to sio/nuvoton/common/.
This mainboard carries 2 local copies. This preparatory patch moves it
out of smihandler.c into a temporary C file to prevent build breakage.
It is to be removed when the shared copy is in place.
WARNING: Disassembly of compiled SMM code shows a possible stack issue.
Do not flash a binary with this patch applied but without the final
shared version above.
Change-Id: I685ebe6c2bb638d815ccf1fcdd1d73edc176c69e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The SHRM firmware load and reset sequence currently runs
unconditionally during the boot process. This causes issues during RAM
dump collection, where the contents of the SHRM region must remain
intact for post‑crash analysis.
This patch adds a Dload‑mode check (which indicates RAM‑dump mode) and
skips shrm_fw_load_reset() when that bit is set. This prevents
unintended SHRM resets during RAM dump capture and ensures the firmware
load/reset sequence only runs during a normal cold boot.
A RAM dump is a debug image used after a crash to preserve system
memory for post‑crash analysis.
Test=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: Ie3d1ff9462a48d21f1daae1f80322ea397731be5
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90651
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for ocicat.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update overridetree.cb with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.
BUG=b:471067114
TEST=Ensure the probed fw_config matches the written configuration.
Change-Id: I6be36f6cec2b7e25b7e6170f12e71ae3fabf283e
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
- Add WIFI SAR table for intel WIFI SAR table
- Follow new UFSC definitions to rename WIFI config
BUG=b:469226622
TEST=Build and flash to DUT, check that SAR table is
loaded by cbmem -1 | grep sar
Change-Id: Iba3c4588c969a74dd83d176124addfa2d115edbd
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Ocicat use ALC3247, and confirm with vendor,
That ALC3247 driver is mapping to ALC236 not AL256.
- Follow ocelot setting, add Audio settings
- Update ALC236 Verb table
- Enable hda codec
BUG=b:469132497
TEST=Flash and boot on DUT, audio works normally
Change-Id: Id60dcaadfefafb499b0555a81192b03b77ad9030
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90518
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sio/nuvoton will soon make use of this for common code. Move the
definition there; mainboard will only set it.
To mitigate possible conflicts in case of multiple SIO chips on
the same mainboard, rename Kconfig to add _NUVOTON_.
Change all existing references to match.
Change-Id: I8e0516411c74b162c31142b02bf5c45e4ca30a1d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89741
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MIPI panel related GPIOs to lb_gpio so Depthcharge can manage panel
reset and power signals when needed.
The following GPIOs are added:
- panel_resx (GPIO_EN_PP3300_EDP_X)
- mipi_iovcc_en (GPIO_EN_PP6000_MIPI_DISP)
- mipi_tp_rstn (GPIO_TCHSCR_RST_1V8_L)
This allows Depthcharge to release reset and disable IOVCC in the
required order to meet the panel power-off timing specification.
[1] Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:461907110
TEST=Boot Padme and check cbmem log is correct.
BRANCH=skywalker
Change-Id: I7f73e41bc4814e8a5ca3579d235001cfafb77bf9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90646
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace AUXADC with FW_CONFIG for storage type detection, and allow
unprovisioned CBI to initialize both eMMC and UFS, providing greater
flexibility for ODMs.
BUG=b:469517374
TEST=boot successfully with both UFS and eMMC SKUs
BRANCH=skywalker
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I400d0a452a5c25b5f429b99bf0b62591ac6cbe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Load I2C firmware to QUPV3_2_SE4 Serial Engine and configure it in
GSI mode to enable ADSP-controlled access to charger and fuel
gauge.
Test=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I58bfe5c65f3dbd2790512c5e013fa7b91cae2933
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Configure and enable the GPIOs required for the USB camera. GPIO 10
(RESET_L) and GPIO 206 (ENABLE) are set as outputs and driven high
during mainboard initialization to ensure the camera is powered on
and ready for use by the OS.
Schematics version: 0.2
BUG=b:453773922
TEST=Verify detection of USB camera using `lsusb` in the OS.
Change-Id: I1f7afcf730f37b1a2e36e3230ae9774508465691
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
We found that our UI resume time will exceed using G2 touch panel. After discussing with vendor they suggested to reduce the stop delay time to 150ms. We can get pass result after this modification. Please see b/468147191 for more details.
BUG=b:468147191
TEST=Pass UI Resume test with G2 touch panel
Change-Id: Iec78e27c4716e3442babad4f377efccb26773183
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC for the Quenbi and Quartz
models. These Qualcomm-based boards require State of Charge (SoC) to be
calculated from dynamic battery metrics because the standard charge
state command is restricted during certain active power states.
Additionally, add platform_dump_battery_soc_information() to romstage
to log the battery percentage early in the boot process. This helps
with debugging power-related issues during the early boot sequence
when serial console is enabled.
Details:
- Select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC for Quenbi and Quartz.
- Call the SoC dump in platform_romstage_main() if CONSOLE_SERIAL is on.
BUG=none
TEST=Boot Quenbi/Quartz and verify "Battery state-of-charge X" appears
in the romstage serial console logs.
Change-Id: I6184762140884762140884762140884762140884
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90619
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both ASRock H110 Pro BTC+ and ASRock Q1900-ITX have their vendor name
spelled as ASRock listed by Memtest86+ when ran on their OEM BIOS. This
patch will restore that vendor name casing behaviour when Memtest86+ is
run from a corebooted port of these mainboards. Cannot verify for the
current mainboards in the repository but this casing is also consistent
with the casing used on the vendor website: www.asrock.com
Change-Id: Icca8a0c0cba4e093a64cc26996de1fb34ee60089
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
8.5MB to accommodate APDP, Ramdump and ADSP-lite images. A 5MB
estimated size of QTEE image is also taken into account to avoid future
resizing.
Size required for QTEE:
Current size -> 2776K, Estimated size -> 5120K (5MB)
Additional size needed -> 5120K-2776K = 2344K
Size required for new images:
Ramdump - 449K
APDP - 0.7K
ramdump_meta - 0.1K
apdp_meta - 1.4K
ADSP_Lite - 1192K
Total = 1643K
Additional size needed (QTEE + new images):
2344K+1643K = 3987K
Current Layout of FW_MAIN_A/B slots:
Total size - 4608K (4.5MB)
Used size - 4126K
Free size - 482K
Additional size needed (excluding free size):
3987K-482K = 3505K
Total size of FW_MAIN_A/B slots:
4608K+3505K = 8133K
An additional buffer of 591K is included in the final size to
provide room for increase in size of other blobs. So,
Final size of FW_MAIN_A/B slots:
8133K+591K = 8704K (8.5MB).
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I3b3ba5c4bf8b5d3830174a890ea7cd089e3f274f
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90594
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move dpm_init() and spm_init() from mainboard_init() in rauru to
soc_init() in mt8196. This centralizes the power management
initialization within the SoC-specific code.
BUG=none
TEST=Build pass, boot ok.
Change-Id: Ic2914fd0fc85032c96ce076416e9b9c46fe19e0d
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90550
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add missing configuration items for rex variants to have functional
MIPI cameras under Windows/mainline Linux:
- Add IPUA device to graphics device configuration
- Add sensor_name register to sensor device configurations
Screebo was missing the gfx/generic configuration for all other display
outputs present in other variants, so add that as well.
TEST=build/boot Win11/Linux on karis and screebo, verify MIPI camera
functional under both OSes using the standard driver stack.
Change-Id: I14ec0efd88c43ca94ebde2be4652775bcb6d73c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Ensure all mipi_camera sensor configurations have both ssdb.lanes_used
and ssdb.link_used defined, and that these values correctly match the
corresponding (known good) CIO2 IPU port configuration:
- ssdb.lanes_used must match cio2_lanes_used = {x} for CAMx
- ssdb.link_used must match cio2_prt[x] for CAMx
Change-Id: Ifbf22c69d29c71138b7f59f08782d90425a09e30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.
TEST=build/boot starlite_adl, verify UEFI DBX able to be successfully
updated via fwupd.
Change-Id: I0fd28e38f5d3ad1e4db33fa3ab075929044ac831
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a CFR option to expose the newly-added EC control to set the charge
LED brightness (normal/dim/off).
TEST=build/boot starlabs/lite_adl, verify charge LED control via CFR
Change-Id: I090437e8de2fd65bfad93a2037fd9346347e9fc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Ali Hamid <ali@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90566
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR options to expose EC controls to set the brightness of the
power and charge LEDs (normal/dim/off).
TEST=build/boot starfighter_mtl, verify LED control via CFR
Change-Id: I2af8372f923f92af62e48da77d4bddb87ab1eba0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90565
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR options to expose EC controls to set the brightness of the
power and charge LEDs (normal/dim/off).
TEST=build/boot starbook_mtl, verify LED control via CFR
Change-Id: I7e1fe4efaab4327c8b95b108a9014e50058d6ed4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90564
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This fixes the duplicate ddr6 entry which should have been ddr5.
Change-Id: I3bbee8a2fbacc7fa057e225fcfe307877b4f2716
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In addition to adding all currently-known names for the boards, add SoC
names to baseboards to make finding boards based on SoC family easier.
Change-Id: I389f68f09409ce3eb51422dbcfe7e80d463a1594
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add support for the new memory Micron MT62F1G32D2DS-031RF WT:C using
spd-3.hex, and MT62F2G32D4DS-031RF WT:C using spd-6.hex
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 0 (0000)
H9JCNNNBK3MLYR-N6E 1 (0001)
H58G56CK8BX146 2 (0010)
K3KL8L80CM-MGCT 3 (0011)
MT62F1G32D2DS-031RF WT:C 4 (0100)
MT62F2G32D4DS-031RF WT:C 5 (0101)
BUG=b:447273470
BRANCH=firmware-trulo-15217.771.B
TEST=util/spd_tools/bin/part_id_gen ADL lp5 \
src/mainboard/google/brya/variants/pujjocento/memory \
src/mainboard/google/brya/variants/pujjocento/memory/mem_parts_used.txt
Change-Id: Ica96fefb3fb8b18ed693383641960c67e128e7e7
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90454
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the touchpad I2C bus high and low time.
BUG=b:466136598
TEST=Build and boot to OS in kodkod.
kodkod:/ # getevent
add device 2: /dev/input/event4
name: "Elan Touchpad"
Change-Id: I5c996ccf69e8dfe1485c7161ea2efd5579190975
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add support for parallel charging by configuring PMC8380F GPIO07
and GPIO09. These GPIOs are configured as outputs with inverted
logic. A new Kconfig option MAINBOARD_SUPPORTS_PARALLEL_CHARGING
is introduced to allow variants to opt-in to this configuration.
BUG=b:468120472
TEST=Build Google/Quartz.
Change-Id: I0126d987650c660e305f704708c09356908633e4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90514
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the qclib_mainboard_override hook to enable Power Delivery
negotiation if no battery is detected, even in normal boot mode.
This allows the system to negotiate higher power levels when
running solely on AC power.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
Change-Id: If1660e4c50575eb4b6d5af606c35accdb4c67982
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
