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mb/google/bluey: Use PMIC for off-mode detection

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Refactor boot mode detection to use is_pon_on_ac() for identifying
off-mode charging, relying on the underlying PMIC registers.
Additionally, introduce is_pd_sync_required() to centralize logic
for enabling Power Delivery negotiation during off-mode, low
battery, or no-battery boot scenarios.

BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.

Change-Id: I7bdece2fc920310f3b1c59a1a6b90cf3bd03e3d9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Kapil Porwal 2025-12-18 19:26:31 +05:30 • committed by Subrata Banik
commit d528561130
1 changed files with 24 additions and 11 deletions
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35
src/mainboard/google/bluey/romstage.c
View file

@ -8,6 +8,7 @@
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/aop_common.h>
#include <soc/pmic.h>
#include <soc/qclib_common.h>
#include <soc/shrm.h>
#include <soc/watchdog.h>
@ -27,16 +28,7 @@ static enum boot_mode_t boot_mode = LB_BOOT_MODE_NORMAL;
*/
bool is_off_mode(void)
{
const uint64_t manual_pwron_event_mask =
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
uint64_t ec_events = google_chromeec_get_events_b();
if (!(ec_events & manual_pwron_event_mask) &&
(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
return true;
return false;
return is_pon_on_ac();
}
static enum boot_mode_t set_boot_mode(void)
@ -53,12 +45,32 @@ static enum boot_mode_t set_boot_mode(void)
return boot_mode_new;
}
static bool is_pd_sync_required(void)
{
if (!CONFIG(EC_GOOGLE_CHROMEEC))
return false;
const uint64_t manual_pwron_event_mask =
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN));
uint64_t ec_events = google_chromeec_get_events_b();
if (!(ec_events & manual_pwron_event_mask) &&
(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)))
return true;
if (google_chromeec_is_below_critical_threshold() || !google_chromeec_is_battery_present())
return true;
return false;
}
int qclib_mainboard_override(struct qclib_cb_if_table *table)
{
if (!CONFIG(EC_GOOGLE_CHROMEEC))
return 0;
if ((set_boot_mode() != LB_BOOT_MODE_NORMAL) || !google_chromeec_is_battery_present())
if (is_pd_sync_required())
table->global_attributes |= QCLIB_GA_ENABLE_PD_NEGOTIATION;
else
table->global_attributes &= ~QCLIB_GA_ENABLE_PD_NEGOTIATION;
@ -75,6 +87,7 @@ void platform_romstage_main(void)
/* QCLib: DDR init & train */
qclib_load_and_run();
/* Underlying PMIC registers are accessible only at this point */
set_boot_mode();
aop_fw_load_reset();