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mb/asus/p8x7x-series: Move CONFIG_SUPERIO_PNP_BASE to sio/nuvoton

Browse source 
sio/nuvoton will soon make use of this for common code. Move the
definition there; mainboard will only set it.

To mitigate possible conflicts in case of multiple SIO chips on
the same mainboard, rename Kconfig to add _NUVOTON_.
Change all existing references to match.

Change-Id: I8e0516411c74b162c31142b02bf5c45e4ca30a1d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89741
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2025-10-24 15:50:16 -04:00 • committed by Matt DeVillier
commit 7273a5b932
8 changed files with 23 additions and 18 deletions
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3
src/mainboard/asus/p8x7x-series/Kconfig
View file

@ -106,8 +106,7 @@ config CMOS_DEFAULT_FILE
config CMOS_LAYOUT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.layout"
config SUPERIO_PNP_BASE
hex
config SUPERIO_NUVOTON_PNP_BASE
default 0x2e
endif

6
src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6776_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6776_ACPI)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
View file

@ -10,9 +10,9 @@
#include <option.h>
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define GPIO0_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
#define GPIO0_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_WDT1_GPIO01_V)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{

2
src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
View file

@ -11,7 +11,7 @@
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/pei_data.h>
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{

6
src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c
View file

@ -5,9 +5,9 @@
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_PNP_BASE, NCT6779D_ACPI)
#define GLOBAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, 0)
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_SP1)
#define ACPI_DEV PNP_DEV(CONFIG_SUPERIO_NUVOTON_PNP_BASE, NCT6779D_ACPI)
void bootblock_mainboard_early_init(void)
{

6
src/superio/nuvoton/common/Kconfig
View file

@ -21,3 +21,9 @@ config HAVE_SHARED_PS2_PORT
port. This one port usually works for keyboards only. Add the nvram option
"swap_keyboard_and_mouse" to cmos.layout to allow changing this port into a
mouse port.
config SUPERIO_NUVOTON_PNP_BASE
hex
depends on SUPERIO_NUVOTON_COMMON_PRE_RAM
help
Set the base port of the super I/O chip.