EINT event mask register is used to mask EINT wakeup source. All wakeup
sources are masked by default. Since most MediaTek SoCs do not have this
design, we can't modify the kernel EINT upstream driver to solve the
issue "Can't wake using power button (cros_ec) or touchpad". So we add a
driver here to unmask all wakeup sources.
TEST=write eint data successfully.
BUG=b:317009620
Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3
Signed-off-by: Chhao Chang <ot_chhao.chang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84025
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
As of commit a911b75848 ("mb/*: Remove old USB configurations from
SNB/bd82x6x boards") USB configurations are drawn exclusively from
devicetree. These stuff should have been removed then.
Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
To ensure we find the correct firmware image, match against `$BOARD":`
rather than just `$BOARD`. This fixes an issue where another board (b1)
using the same firmware build or name as the one we are searching for,
causes the grep matching to return empty strings.
TEST=successfully extract the firmware image for CAREENA, which
previously failed.
Change-Id: I2f2a71f0b033938aafc1fd27e2996fe319614b3c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit fee8bcbcfb ("drivers/asmedia: Add code to enable AHCI for
ASM1061") renamed the ASMEDIA_ASPM_BLACKLIST Kconfig to ASMEDIA_ASM_1061
since the former was only ever used for that card.
However, commit fb24620534 ("mb/asrock: Add Z87 Extreme4 (Haswell)")
was merged first and used the old Kconfig, so the tree broke when the
AHCH patch was merged. Change the Kconfig to fix the tree.
Change-Id: If16455c43e583e7edbf7914db87346385d811190
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86056
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ASMedia ASM1061 seems to default to IDE mode, which seems to be the
source of payloads and Linux not recognizing/booting from drives
connected to it. From the behaviour of vendor firmware on the ASRock Z87
Extreme 4, the mode can be changed by setting the PCI Subclass register
to either 0x06 (SATA controller) or 0x01 (IDE controller). This register
seems to be read only, but can be unlocked for writing by setting bit 2
at offset 0xEC in the PCI config space.
Since the ASMEDIA_ASPM_BLACKLIST driver already existed and only matched
the ASM1061, rename it to ASMEDIA_ASM1061 and add the AHCI mode setting
code to it. To maintain consistency with chipset SATA ports, this is
also configurable through the existing sata_mode CMOS option with the
default set to AHCI.
Tested on the ASUS Maximus VI Gene.
Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Enables onboard LEDs for power and reset button as well as flash chip
indicator LED. Also enables POST code display. Both LEDs and PCD turn
on when the system is powered and turn off once the payload is reached.
This mimics the behavior on vendor firmware.
Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List an additional USB debug port on one of the USB-2.0-Headers.
Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add various previously missing settings as well as a few devices,
also tidy up the comments and make whitespace consistent.
Tested on hardware, no regressions were observed.
Mainboard boots Arch Linux with EDKII payload, S3 suspend and
resume works, as before.
Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86006
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- D-Sub Port
- DVI-D Port
- HDMI Port
- RJ-45 Gigabit LAN Port
- All four rear USB 2.0 Ports
- All four rear USB 3.1 Gen1 Ports
- Both USB 2.0 headers
- USB 3.1 Gen1 header
- All six SATA3 6.0 Gb/s connectors by Intel
- Both PCI Express 3.0 x16 slots
- PCI Express 2.0 x16 slot
- PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not (yet) tested:
- IR header
- COM Port header
- eSATA connector
- PS/2 Mouse/Keyboard Port
Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85884
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection via jumper and onboard Power and Reset switches.
Special thanks to Angel for enabling various LEDs/PCD functions!
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- HDMI-Out Port
- DVI-D Port
- RJ-45 Gigabit LAN Port
- Both USB 2.0 Ports
- All four USB 3.1 Gen1 Ports
- All three USB 2.0 headers
- Both USB 3.1 Gen1 headers
- Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH)
- All six SATA3 6.0 Gb/s connectors by Intel
- All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU)
- Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not (yet) working:
- both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 (fix will soon
be merged)
not (yet) tested:
- IR header
- COM Port header
- DisplayPort
- eSATA connector
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84672
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- D-Sub Port
- DVI-D Port
- HDMI Port
- RJ-45 Gigabit LAN Port
- Both rear USB 2.0 Ports
- All four rear USB 3.1 Gen1 Ports
- Both USB 2.0 headers
- USB 3.1 Gen1 header
- All six SATA3 6.0 Gb/s connectors by Intel
- Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU)
- PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not (yet) tested:
- PCI slots
- IR header
- COM Port header
- PS/2 Mouse/Keyboard Port
- Optical SPDIF Out Port
Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85926
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- HDMI-Out Port
- DVI-D Port
- D-Sub Port
- RJ-45 Gigabit LAN Port
- All four USB 2.0 Ports
- All four USB 3.1 Gen1 Ports
- Vertical Type A USB 3.1 Gen1 (located next to RAM slots)
- All six SATA3 6.0 Gb/s connectors
- PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU)
- PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU)
- Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not working:
- Both USB 3.1 Gen1 headers (also not working on vendor firmware,
possible hardware defect)
not (yet) tested:
- IR header
- COM Port header
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When writing key_protect_setting to PMIC, PMIC expects receiving 1 byte
per write. PMIC would receive unexpected zero byte if using
mt6685_write16. Fix the write operation by using mt6685_write8.
TEST=Build pass.
BUG=b:388666377
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86035
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the issue where the DUT cannot power on during S5. When writing
key_protect_setting to PMIC, PMIC expects receiving 1 byte per write.
PMIC would receive unexpected zero byte if using mt6363_write16. Fix the
write operation by using mt6363_write8.
TEST=Build pass, DUT can power on during S5.
BUG=b:388666377
Change-Id: I0a7c0d2fa1f93a55731b4b58923d6f80a4c4be89
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86034
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from SPM: 0, non-SPM: 0x1.
In MT8196, SPM has masked all the DDR requests, so this setting should
be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will
hang when accessing DRAM.
BUG=b:379039600
TEST=boot up ok, GCE can access DRAM continuously
Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
In the current eDP initialization flow, eDP is configured and enabled
before display data pipe (DDP) initialization. The init flow is wrong,
because eDP should be enabled only after DDP is correctly set up. The
wrong flow may lead to garbage display between enabling eDP and
configuring DDP.
To fix the problem, the dptx_video_enable(true) call needs to be moved
after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP
enablement, to be separated from the existing mtk_edp_init(). The fixed
eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable.
Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86028
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run mtk_fsp_romstage.elf (MediaTek firmware support package for
romstage) in romstage to support power switch.
BUG=b:373797027
TEST=build pass, boot ok.
Load and run mtk_fsp with following logs:
[DEBUG] FMAP: area FW_MAIN_A found @ 402000 (1527552 bytes)
[INFO ] CBFS: Found 'fallback/mtk_fsp_romstage' @0xfc280 size 0x6bd in
mcache @0x00122518
[INFO ] VB2:vb2_digest_init() 1725 bytes, hash algo 2, HW acceleration
enabled
[INFO ] _start: MediaTek FSP_ROMSTAGE interface version: 1.0
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase
0x30 done
Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86015
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers,
each with a different number of EINT bits. In preparation for the
upcoming MT8196 EINT unmasking support, replace the `eint_event_reg`
struct (which has a hardcoded register number) with an array
`eint_event` to specify the EINT base register(s).
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86033
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load MCUPM firmware and boot up MCUPM in ramstage.
It takes 54 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308
mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes)
TEST=Build pass and we can see the mcupm logs after reset releases.
BUG=b:317009620
Change-Id: I223f245d384f32d54f6170a28b29573638f77296
Signed-off-by: Agogo Huang <agogo.huang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This resolves a crash issue observed on Meteor Lake and introduced by
commit 70bdd2e1fa ("cpu/x86/topology:
Simplify CPU topology initialization"). This commit simplifies the
code and provides more detailed CPU topology information by
generalizing the use of the Extended Topology Enumeration Leaves
0x1f. As a result, the coreboot APIC core_id field does not provide
the fully detailed path information.
It turns out that the topology core identifier is used by the coreboot
MP service mp_get_processor_info() implementation. But the MP Service
EFI_CPU_PHYSICAL_LOCATION data structure only captures information
about the package, core, and thread. The core identifier returned to
the MP service caller must incorporate the full hierarchical path (die
group, die, module, tile, module and core).
This commit adds a new field to the cpu topology structure to
represent the core ID within the package.
For reference, here is that signature of the crash:
LAPIC 0x40 in X2APIC mode.
CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
Code: 0 eflags: 00010046 cr2: 00000000
eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
[...]
The crash occurred when FSP attempted to lock the Protected
Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
0x4e).
69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax
69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp)
69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp)
69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx
69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax
69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx
69f3d1e5: 0f 30 wrmsr
69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39
FSP experiences issues due to attempting to lock the same register
multiple times for a single core. This is caused by an inconsistency
in the processor information data structure, where multiple cores
share the same identifier. This is not permitted and triggers a
General Protection Fault Exception.
TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex
board.
Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86004
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Improve host EC command debugging with timestamps and duration for
better analysis, this feature can be enabled by selecting the config
EC_GOOGLE_CHROMEEC_HOST_CMD_DEBUG.
BUG=none
TEST=Brox/lotso device successfully built and booted. Debug messages
confirmed in device logs only when the specific configuration is
selected. Sample print: "EC HOST CMD Duration: 661 us, Command: 0x4b,
version: 0x0"
Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch selects the ISH main firmware Kconfig to prevent
google/fatcat from trying to retrieve a dummy ISH SHIM firmware version,
since ISH FW in google/fatcat will be part of the kernel firmware image.
BUG=b:370984186
TEST=Build and boot google/fatcat, config exists in coreboot.config
Change-Id: Id24394cb6c6dbaed13c87612da341e47eb69895f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85920
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit e24294ff9ade ("lsusb -t: print ports and busses and devices with
same width") [1] in the usbutils repository changed the format of the
lsusb -t output, breaking the find_usbdebug.sh script. This commit is
present in usbutils version 016 and later.
Use the output of lsusb -V to set the parsing patterns based on the
version in order to maintain compatibility with older versions of
usbutils. A simple integer comparison of the version number is used for
this, which will not work with versions older than v001 as those use a
0.nn version number format. However, since v001 was released in late
2010, it is probably safe to assume that no one will be using a version
of usbutils older than that. Usbutils v016 was released in late 2023 so
there could still conceivably be systems using older versions, such as
Ubuntu 22.04 LTS which is on v014.
TEST=find_usbdebug.sh works as expected with both lsusb v015 and v017
[1] e24294ff9a
Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85790
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since Python 3.12, invalid escape sequences produce a SyntaxWarning;
in the future, they will produce SyntaxError.
Using raw strings clear out the warning.
Below the command used for checking the fix worked.
```
$ python3 util/lint/checkpatch_json.py
```
Link: https://docs.python.org/3.12/whatsnew/3.12.html#other-language-changes
Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7
Signed-off-by: Ariel Otilibili <otilibil@eurecom.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85771
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
While I don't have +2 rights, I think it makes sense to add myself as
maintainer given I'm a creator of both ports in upstream tree.
Change-Id: I2484fc488040c2d86bbf3bf98f39354bf88efae8
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add a check to make sure lsusb and lspci are installed, as the script
relies on them to function properly. Previously, if lsusb was not
installed, the script proceeded as if nothing was wrong, but never found
any devices plugged into the debug port. If lspci was not found, the
script exited saying that no EHCI debug capable controller was found.
The "command not found" messages that normally would have been shown in
these situations was not being shown, as stderr is redirected to
/dev/null to hide error messages that don't matter as per the comment
near the top of the script.
Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit ce10b6f821 unhid the BOOT0000
device from Windows. It requires a driver that's available from Coolstars EC bundle.
Guard this against the ChromeEC, so that non-Chromebooks don't get an
error device in Device Manager.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rather than unconditionally returning that the device is present,
return whether the fTPM is on or not.
Test=Boot the StarLite Mk V with the Intel ME disabled, and check
that the TPM is reported as not present.
Change-Id: If8236021bf0e1264646971cff9c998fac99ac220
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85228
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The CLFR method exists outside the CNVi device, so add `^` to allow
it to be found. This fixes the SSDT and allows the method to be used.
TEST=build/boot starlabs/starlite_adl
Change-Id: I1158cf1ccf50d9095fdab8d2d663041ef1985513
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in 377955793#comment20
BUG=b:377955793
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0455d62a9f174fd911e5aa0b9626329ad2ac8f06
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86000
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
