Linux has never supported this feature, and according to our FAE, the
Windows driver dropped support for it in 2022 so remove it.
Change-Id: I4f0b6108bb5db657490a8b9395bb99378fc63c4d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add support for RTD3 for Intel Bluetooth. This is done by
controlling the enable GPIO (GPP_VGPIO_0 for most SOCs) that
exists on all wireless cards since Jefferson Peak.
The exception is GalePeak2, which uses VSEC and this driver doesn't
support that.
Change-Id: Ibea97ab0ae0a9f1eb6aaca43d831bb4ce7bdc02e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Print a warning when the FSP UPD for CNVi Audio Offload is enabled
without the corresponding USB ACPI driver being enabled.
Throw an error when the USB ACPI driver is enabled without the
corresponding UPD being enabled.
Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add AOLD Method, which returns an integer based on
whether Audio Offload is enabled. Leave the existing
control of Audio Offload in `soc/soc_chip.h`. Add
`cnvi_bt_audio_offload` in the USB ACPI `chip.h` to
control the aforementioned return value.
The value in `soc/soc_chip.h` and `chip.h` should
match.
Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84134
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to CB:68982, add SPDX license headers to rex template
Makefile. Without this patch, build bot may report build failed.
BUG=none
TEST=Run create_coreboot_variant.sh and check Makefile
Change-Id: I7d100a2303be063590f1389a7eed8f9a52071241
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change reiterates that the coreboot leadership may revoke a user's
privileges. This does not change anything, as it already says "The
community organizers may take any action they deem appropriate, up to
and including a temporary ban or permanent expulsion from the community
without warning".
Also add a note that the discussions are private. If someone wants to
make the issue public, the coreboot leadership can't stop them, but the
board believes in handling these issues privately.
Finally, add a note that if there's an issue with someone on the
arbitration board, issues may be taken directly to the leadership board.
Change-Id: I5e2010a16f31f892bd1761b56b96ea773877dea0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The original URL now points to "AMD Documentation Hub" and not the
document.
Change-Id: Icc42943340132843df2387cc1203178a0774a387
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add targeted feature list for Xeon 6 coreboot. The listed features
are targeted to be supported by Xeon 6 coreboot design, while some
specific items might need fixes and improvements per community
feedback.
Change-Id: Ibecd63dfca10712223ccdd943109ba28ed668200
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84701
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When validating the FMAP against the IFD, the BIOS region is a somewhat
specical case, since the FMAP BIOS region usually does not match the IFD
BIOS region. Instead the FMAP region usually resides somewhere inside
the IFD BIOS region and the where depends on CONFIG_CBFS_SIZE.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I920a0ee246cfd2b4ae0870256357d4f285e1730d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Because we import the doimage_mv/Makefile.mk directly into the main
coreboot makefile, this was setting a global CFLAGS variable. That's not
a huge issue since coreboot doesn't use the global CFLAGS variable, but
it should be updated anyway.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iebe281ca891745c1f993df274ef75b1440059c85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
After CB:76315, TPM_RDRESP_NEED_DELAY, whose historical mission has
ended, could be removed.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I51e046fb738d2ff7a23225739de62a1a7780bc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
TPM_RDRESP_NEED_DELAY was introduced in 2018 in CB:25322 after
observing errors with SLB9635 by Infineon. It has been confirmed
also SLB9670 and SLB9672 require a fix or delay here.
Presumably, prior to CB:4388 SLB9635 did not have this problem,
as this particular TPM shipped with samsung/lumpy Chromebook since
2011. In CB:4388 the code changed from polling the status register
(+burst_count) using a 32bit read to separated 8bit reads.
So far, experiments on samsung/lumpy and SLB9635 indicate that
it would be sufficient to add a single tpm_read_status() call
to see TIS_STS_DATA_AVAILABLE as set at the time of evaluating
the loop exit condition.
Change-Id: If5c3e93c7946ebf8226f7bba47b38253f6920c61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Co-authored-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In order to fit the specification, change gpio setting for touch panel
and wwan.
Change items:
1. wwan : Add WWAN_RST_L to 0. And we want WWAN_EN to pull high more
early than WWAN_RST_L, so add WWAN_EN to 1 in romstage stage.
2. touch panel : First we add EN_PP3300_TCHSCR and USI_RST_L to 0 to
init status. And we want EN_PP3300_TCHSCR to pull high more early than
USI_RST_L so delete USI_RST_L pull high in romstage.
BUG=b:357764679
Test=emerge-nissa coreboot
Change-Id: I0a07ea8e2bf3d165dcebd89c4c564f157d9d4846
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84668
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting devices to unprovisioned allows us to perform
functional testing without having to rewrite the fw config
during the SMT phase of factory production.
BUG=None
TEST=Build lotso firmware and boot to OS when fw_config is
unprovisioned and ensure all devices are enable.
Change-Id: I3b8285ce335ee0f3595d184eb0921f697bdbd0c2
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84714
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Since the Kconfig default for boolean options is already 'n', there's no
need to add that default to the option. Still kept the 'default n' for
the 3 options that result in fuses inside the SoC to be burnt
(PERFORM_RPMC_PROVISIONING, PERFORM_SPL_FUSING and
PSP_PLATFORM_SECURE_BOOT) to point out the fact that that's not selected
by default more clearly.
Change-Id: I55971f1f130d8ec23d4572a215008d9465e1520a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add the data structures used for the command buffers for the PSP SMI
commands to increment and request the state of the monotonic counters in
the SPI flash. These data structures are specific to the PSP SMI mailbox
interface and not the data structures from the RPMC specification. The
AGESA code was used as a reference.
Change-Id: I8bc8ff4cf9b7ebd0e034f040dde2db8385bb8f79
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes:
pcieport 0000:00:06.0: can't derive routing for PCI INT D
pcieport 0000:00:06.0: PCI INT D: not connected
PEG1 should also be PCI_INT_B.
Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.
Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Windows driver only checks PCI0, so move the window accordingly
so that it can be used.
Tested on `starlite_adl` by booting Windows 11 installation medium.
Prior to this patch, it would flag that the security requirements
were not met - it now happily installs.
Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This pin is used by the DisplayPort connector for Hot Plug.
Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override the PL4 to the maximum power the battery can provide
without a charger connected to prevent drawing too much power.
Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The wrong definition was used, so the code had no effect.
The ID for the processor used is `b06e0`.
Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards use hubs for devices, so correct the ACPI configuration
for these ports. Also, add more information to the comments for the
ports.
Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Make the I2C speed user configurable from CMOS. Both the touchscreen
and accelerometer support running at 100MHz or 400MHz. They perform
better at 400MHz but use more power - this patch lets the user choose.
Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This method is used to provision the CNVi, and ensure
that it is in the correct state.
Intel document #559910 details this.
Change-Id: Id8a36a09c7beaf3ba8b29d3276bd9dc59420dab5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83713
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method is used to limit frequencies on CNVi.
Intel document #559910 details this.
Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must
exist to avoid a BSOD on Windows.
Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add a general purpose handle to allow CNVi to be notified
of state changes.
Intel document #559910 details this.
Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a _PRR method that the OS can use to reset the wireless.
This is only used for integrated solutions and depends on the
CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new
ACPI is added, the behavior of existing boards won't be
changed unless they configure the accompanying Bluetooth device.
Intel document #559910 details this.
Change-Id: I25e8462780badcad88b13052a6eb282c83af5def
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
All CNVi modules, integrated or dedicated only support D3 Hot
so add _S0W to limit the sleep state.
Intel document #559910 details this.
Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
These fields are used to monitor events on CNVi.
Intel document #559910 details this.
Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
The CNVi driver is relatively basic in coreboot and most
noticeably, recent Linux kernels flag that lack of a _PRR
method, which is used to reset WiFi and Bluetooth.
This patch series adds methods recommended by Intel in
document #559910.
This patch defines an OpRegion for CNVi, for both
integrated and dedicated solutions.
Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook up CNVi Bluetooth UPDs to the devicetree. Set CnviBtCore to
`true` so the current behaviour is not changed.
Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84596
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of these boards support or use S0ix so c6dram isn't needed, so
disable it.
Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is only 1 Type-C port, the rest are Type-A.
Tested on Linux by verified the correct names are shown in dmesg.
Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Port 2 is a hub, used for the internal keyboard and the card reader.
Adjust this to a hub.
Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
The existing GPIO configuration was IRQ heavy; tweak this to reduce
the number of interrupts.
Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A debug configuration was left in the patch when it was uploaded,
remove this.
Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
The wireless GPIOs don't need to be configured in the bootblock,
so set them up in ramstage.
Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The first table from the chapter 4.1 'OP1/OP2 Command Definition: No
Address Phase' of the JEDEC standard JESD260 (Replay Protected Monotonic
Counter (RPMC) for Serial Flash Devices) in the version from April 2021
was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0050aea6cdc537122bae63fddb417dd9f6b75a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
