Documentation/soc/intel/xeon_sp: Add targeted feature list
Add targeted feature list for Xeon 6 coreboot. The listed features are targeted to be supported by Xeon 6 coreboot design, while some specific items might need fixes and improvements per community feedback. Change-Id: Ibecd63dfca10712223ccdd943109ba28ed668200 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84701 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -19,6 +19,90 @@ The supported platform status are as below,
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- Buildable and bootable with real FSP headers/binaries
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## Targeted features list
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1. ACPI
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- RSDP/RSDT/XSDT/FADT/FACS/DSDT/SSDT
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- MCFG/MADT/SRAT/SLIT/HMAT/DMAR/CEDT
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- HEPT/SPMI/TPM2
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- HEST/EINJ/ERST/BERT
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2. SMBIOS
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- Type 0 - BIOS information
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- Type 1 - system information
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- Type 2 - base board information
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- Type 3 - chassis information
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- Type 4 - processor information
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- Type 17 - memory device
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3. Hardware related
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- Basic PCIe support
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* IIO bifurcation
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* PCIe hot plug
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* VT-d
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- Customizable PCIe host bridge bus/MMIO resource window size for smart NIC support
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* To handle the case where a large amount of PFs/VFs will be presented under specific PCIe host bridge
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- On-Chip accelerator (QAT, IAA, DSA, DLB)
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- CXL 2.0 Type-3 memory
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- NUMA and sub-NUMA clustering
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- GPIO (with physical pins)
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- Virtual GPIO
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* eSPI based, use BMC or CPLD to expand GPIO pin counts on PCH-less SoC
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- BMC support
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* IPMI KCS
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- Power Sequence
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* ACPI S0/S5
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* Fast cold/warm reset
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- CPU OSPM
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* OS native (based on intel p_state/intel_idle OS driver)
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- RAS
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* Based on FSP2.4 FSP-SMM
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* APEI support
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* Memory CE/UCE (firmware first mode, e.g. MCA/eMCA)
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* IIO CE/UCE (firmware first mode, e.g. DPC/eDPC)
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4. Firmware related
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- Boot to various payloads (Linux payload/TianoCore/UniversalPayload)
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- Enlarged CBFS (>16MB) for one or multiple cloud payloads
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- VPD
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## Build steps
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### Prepare workspace
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