Add driver to read 'hwid' file from CBFS and use it for SMBIOS product
name. Processes the ChromeOS-format HWID string by removing prefix
after colon, trimming whitespace, and extracting base name before
any hyphen/space. Returned string is normalized to have the first
character/letter capitalized, and the rest lower case. If no HWID file
is found in CBFS, the fallback is CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME.
This driver is intended to allow ChromeOS devices running upstream
coreboot to persist their board's unique HWID and use it as the SMBIOS
board name, but it is not limited to that function.
TEST=tested in MrChromebox downstream. Multiple devices which use the
same ChromeOS board but differ in HWID can use the same firmware image
and still be properly identified.
Change-Id: I1af1df4c79858d23ef71400abe72f41eec6c25c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
We used to put SMBIOS header and other data before VPD. That is not the
case anymore. New device will write the VPD starting at 0 instead of
0x600. Search VPD at 0x0 to support this.
TEST=build and boot google/geralt. VPD is found both at 0 and at 0x600.
Change-Id: I7072f7c646b6b55d11bc06dba5674828246fa1d0
Signed-off-by: Jian-Jia Su <jjsu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add a new Kconfig option, FSP_VGA_MODE12_MONOCHROME, to allow the
system to use a 1-bit-per-pixel (1bpp) planar VGA buffer during FSP
initialization instead of the standard 4bpp buffer. This is useful
in romstage where every byte is critical.
When this option is enabled, the FSP is expected to handle the
internal replication of the 1bpp data across the other three
color planes to render the monochrome image.
Key changes:
- Introduce FSP_VGA_MODE12_MONOCHROME Kconfig option.
- Automatically select FSP_VGA_MODE12 when the monochrome option is
used.
- Set FSP_VGA_MODE12_BPP to 0x1 when FSP_VGA_MODE12_MONOCHROME is
selected.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Ie77c40025c13e52188439fffedc834c26338bfe3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When updating clang to version 21.1.5, we now get the following error
when compiling the CFR code.
```
src/drivers/option/cfr.c:287:19: error: default initialization of an
object of type 'struct sm_object' with const member leaves the object uninitialized
[-Werror,-Wdefault-const-init-field-unsafe]
287 | struct sm_object sm_obj_copy;
```
In this specific case its actually not an issue, but initialize the
variable from the start to avoid the error and arguably make the code
easier to read.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib0b22e20a7482ab29d997a3e3c3bec4a1db1a4f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89958
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no reason I can think to also pass the old object into the
constructor considering that the new objects contains the exact same
contents during that call (it's copied over a few lines above).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idd5b34134b6064c19266448b551248eb29e097fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89957
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add ACPI power state methods (_PS0, _PS3, _S0W, _S3D) to the GFX0
device definition to fix VIDEO_TDR_FAILURE 0x116 errors when
resuming from S3 sleep under Windows on modern Intel platforms
(TGL and newer).
Windows requires these methods to properly manage GPU power states
during sleep/resume cycles. Without them, Windows cannot determine
the correct power state transitions, leading to display driver
timeouts on resume.
The methods are implemented as no-ops since integrated graphics
power is managed by the platform, but Windows needs the method
definitions to properly initialize and restore the GPU after S3
resume.
TEST=build/boot starlabs/starlite_adl, verify S3 resume from
Windows works properly without a VIDEO_TDR_FAILURE BSOD.
Change-Id: Ib3f8060dee3281c2281d4e719be9aff9e0239b49
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90013
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently we may return an undefined pointer called
`none_driver_config` since stack variables are not by default
initialized to 0/NULL.
This also causes an issue when updating to a clang version 21.1.5 from
version 18.1.8, since it complains about this very issue.
returning NULL is fine, since the macros in this file actually depend on
it to figure out where to get the config from.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b719ca9fd41409375f635b1dcddbc5796b48fe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enables correct identification of boards using tas2563 speaker amplifier
by SOF Windows drivers.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I7dd0276a44ebb9b0712589c28ac017bff1ed5b1a
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89878
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel.
This was tested on the fatcat/variants/ruby mainboard to ensure
that the SSDT contained the equivalent parameters that are provided
by the current DSDT object.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I801ef13937078ca9cfcd3610b1aa8aaedbaf1cf1
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
Add a mechanism for mainboards to override default values of CFR
objects defined in SoC or common code without duplicating object
metadata.
Mainboards can now declare a simple override table mapping option
names to new default values:
const struct cfr_default_override mb_cfr_overrides[] = {
CFR_OVERRIDE_BOOL("s0ix_enable", false),
CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
CFR_OVERRIDE_END
};
The CFR backend checks this table when writing options and uses the
override value if one exists. All other metadata (name, help text,
enum values, flags) comes from the original object.
Change-Id: Ifb3da90d605f2799bf0207ff58d69bee3415ccc2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89933
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds new Kconfig options and a code snippet to support
VGA mode 12 within the FSP (Firmware Support Package) 2.0. The
changes allow platforms to select VGA mode 12 and configure it.
The key features are:
- Introduces `FSP_VGA_MODE12` to enable VGA mode 12 support.
- A new `FSP_VGA_MODE12_BPP` option defines the bits per pixel,
defaulting to 4 for color mode.
- A bitmap buffer is allocated on the stack and supplied to FSP
based on the configured bits per pixel.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Iaa3a64b7c8c735d8329b3596f4be315871bc7fa4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit ddf5987c1e ("drivers/mipi: Add support for
TM_TL121BVMS07_00C panel") (CB:89216) added support for the
TM_TL121BVMS07_00C panel, but the screen was not functional.
Decrease the pixel clock from 4,400,560 Hz to 264,355 Hz to match the
actual panel timing specification. Also, the panel uses C-PHY interface,
so enable the `PANEL_FLAG_CPHY` flag accordingly.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:428854543
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: I88fa5215d7596926aa95a58ae91dd6ade793388b
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89568
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change adds a null pointer check to ensure that the SoC-specific
function to retrieve I2C bus speed is properly mapped before attempting
to call it. Without this check, systems may crash during boot when the
function pointer is not initialized. The issue occurs when the
touchscreen or touchpad is configured to use THC-I2C via CBI fw_config,
but the underlying SoC doesn't provide the required I2C speed function
implementation.
BUG=none
TEST=Boot Fatcat board to OS with CBI fw_config selecting touchscreen or
touchpad using THC-I2C. Verify no crash occurs during boot and touch
devices function properly.
Change-Id: Ib982f4435aa506f2b9203f81140366addc6559f3
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
CS42L43 contains a range of optional properties which control the
behaviour of jack and accessory detect, and are added here.
These properties are documented in the Linux kernel source code, in the
file:
linux/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml
which contains names, descriptions, valid and default values.
Being optional, these properties will be ignored if not specified.
Change-Id: I53fbed81df9157022384d5879c9d9ed351641ab5
Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it. Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.
More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
This was initially tested on Talos II (OpenPower platform) by Raptor
Computing Systems. Later versions were tested using QEMU and ipmi_sim
from OpenIPMI project as well as QEMU's builtin BMC simulator.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67057
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Complies with the Multi-Processor (MP) service as defined by the
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in the Platform
Initialization Specification 1.7. If bit 24 (CPU_V2_EXTENDED_TOPOLOGY)
is set in ProcessorId, GetProcessorInfo() must populate the
EFI_CPU_PHYSICAL_LOCATION2 data structure.
TEST=FSP using PI 1.7 GetProcessorInfo() is able to retrieve the
information instead of receiving an EFI_NOT_FOUND error.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d65
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89462
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Enhancements have been made to the Intel touch driver, including support
for Google touchscreen devices, ELAN9006 and ELAN6918. The update
also includes device-specific configuration changes for both I2C and SPI
interfaces.
Key improvements include:
- Google Touchscreen support integration for ELAN9006 (SPI) and ELAN6918
(I2C).
- Specification of recommended connection speeds for supported devices.
- Removal of an unnecessary 100ms delay in the SPI _RST method.
- Addition of a function to map the System on Chip's (SoC) I2C speed
frequency.
- Improved device-specific connection speed settings for both I2C and
SPI interfaces.
These changes aim to improve the driver’s compatibility and efficiency
when interacting with the newly supported devices.
BUG=none
TEST=Test the updated driver on devices using ELAN9006 and ELAN6918 to
verify improved responsiveness and correct device initialization.
Confirm that connection speeds are set as recommended and check the
absence of the previously unnecessary delay in SPI operations from the
SSDT.
Change-Id: Ie35de90ece44101aea008d13d19e12873cdc09bf
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch extracts the implementation responsible for retrieving DIMM
information from the FSP HOBs and centralizes it within the common FSP
driver code.
This ensures that each SoC layer does not duplicate the logic for
parsing memory-related data. The primary goal is to rely on the
common FSP driver code for retrieving memory information.
The only SoC-specific implementation that remains is limited to
handling dependencies related to FSP UPD or header differences across
SoC generations.
TEST=Able to build and boot google/kinmen. Verify the memory related
information is proper as part of the SMBIOS table.
Change-Id: Ic3741a248bb1fe9420c784d51fbf459a30f8c42f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89494
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to QEMU docs/specs/fw_cfg.rst, the selector and data register
offsets of Arm & RISCV should be 0x8 and 0x0. Besides, the selector
register should be in big-endian when using MMIO access.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt -bios build/coreboot.rom -nographic
-drive if=pflash,file=./build/coreboot.rom,format=raw".
Change-Id: I1c4d40a4dbcac4067a7c69ba916e6ff0a21cdcb6
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add support for Class-D Smart Amplifiers: CS35L56, CS35L57 and CS35L63.
CS35L56 and CS35L57 are 18.5 V Class D Smart Amplifiers with Multi-Cell
Battery Boost.
CS35L63 is a PC Smart Amplifier with Speaker Protection and Audio
Enhancement Algorithms.
The driver was written based on the Datasheets for these parts and
generates the audio SSDT information for the amplifiers. Since all
three parts are part of the same family they all have similar SoundWire
settings.
The user can configure which part, SSID and Speaker ID is generated in
ACPI, as well as define each amplifier's Soundwire Unique ID and Link
ID.
These parts support DisCo Version v2.1, but coreboot currently only
supports DisCo v1.0, so ACPI is only generated based on DisCo v1.0.
These parts also support the SDCA v1.0 Specification (from DisCo v2.1)
is also not currently supported by coreboot, therefore SDCA ACPI
properties are also not generated.
This is currently only tested using QEMU using example configuration:
chip drivers/soundwire/cs35l56
# SoundWire Link 2 ID 3
register "desc" = ""Left Speaker Amp""
register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
register "sub" = ""12345678""
device generic 2.3 on end
end
Which produces the ACPI:
Device (SW23)
{
Name (_ADR, 0x00023301FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0F)
{
Package (0x02)
{
"mipi-sdw-sw-interface-revision",
0x00010000
},
[...]
Package (0x02)
{
"mipi-sdw-source-port-list",
0x18
},
Package (0x02)
{
"mipi-sdw-sink-port-list",
0x06
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x06)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
},
Package (0x02)
{
"mipi-sdw-dp-0-subproperties",
"DP0"
},
Package (0x02)
{
"mipi-sdw-dp-1-sink-subproperties",
"SNK1"
},
Package (0x02)
{
"mipi-sdw-dp-2-sink-subproperties",
"SNK2"
},
Package (0x02)
{
"mipi-sdw-dp-3-source-subproperties",
"SRC3"
},
Package (0x02)
{
"mipi-sdw-dp-4-source-subproperties",
"SRC4"
}
}
})
Name (BRA0, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x04)
{
Package (0x02)
{
"mipi-sdw-bra-mode-min-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-data-per-frame",
0x01D6
},
Package (0x02)
{
"mipi-sdw-bra-mode-min-us-between-transactions",
Zero
}
}
})
Name (DP0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x07)
{
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x01)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
}
}
})
Name (SNK1, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0C)
{
Package (0x02)
{
"mipi-sdw-data-port-type",
Zero
},
Package (0x02)
{
"mipi-sdw-max-grouping-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-imp-def-dpn-interrupts-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-modes-supported",
One
},
Package (0x02)
{
"mipi-sdw-max-async-buffer",
Zero
},
Package (0x02)
{
"mipi-sdw-block-packing-mode",
One
},
Package (0x02)
{
"mipi-sdw-port-encoding-type",
One
},
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
Package (0x02)
{
"mipi-sdw-simplified-channelprepare-sm",
Zero
},
Package (0x02)
{
"mipi-sdw-port-channelprepare-timeout",
Zero
},
Package (0x02)
{
"mipi-sdw-channel-number-list",
Package (0x02)
{
Zero,
One
}
},
Package (0x02)
{
"mipi-sdw-channel-combination-list",
Package (0x01)
{
0x03
}
}
}
})
Name (SNK2, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC3, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC4, Package (0x02)
{
[... same as SNK1 ...]
})
}
Change-Id: Ie04020f008862051f26e0101828b5944d212e706
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add TM panel TM_TL121BVMS07_00C serializable data to CBFS.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.
[INFO ] CBFS: Found 'panel-TM_TL121BVMS07_00C' @0x81f80 size 0x77
in mcache @0xfffdd540
BUG=b:428854543
TEST=build and check the CBFS include the panel
BRANCH=skywalker
Change-Id: I50e56aef1576722b7f2fb811c5d9df2a5697edae
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89216
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The header guard comment in the chip.h file was incorrect, using
_GENERIC_WIFI_H_ instead of the correct _WIFI_GENERIC_H_. This
commit corrects the typo to ensure consistency.
Change-Id: I00a93e811608ddf449065bc92441648f7332fc4b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89055
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Moves the MTRR setup for graphics memory (GMADR) from the
`soc_load_logo_by_coreboot()` function to `do_silicon_init()`. This
refactors the logic into a new helper function,
`soc_mark_gfx_memory()`, which acquires a temporary Write-Combine
(WC) MTRR.
The MTRR is now configured earlier in the silicon initialization
process, making the setup and cleanup independent of the
`soc_load_logo_by_coreboot()` function itself.
This improves FSP-S performance and ensures the MTRR is correctly
managed within the silicon initialization flow which was earlier
missed when platform selects `USE_COREBOOT_FOR_BMP_RENDERING` aka
rendering the BMP logo using coreboot driver and not using FSP driver
logic.
The cleanup of the MTRR is also moved to `do_silicon_init()` to pair
with the earlier setup.
TEST=Successfully boot to OS on google/fatcat using coreboot for logo
rendering.
w/o this patch
```
963:returning from FspMultiPhaseSiInit 1,164,839 (123,244)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,143,974 (115,443)
```
Change-Id: I5da3178c622f5fd6cb3d7f3f574e59f9ed5a5b3d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88982
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.
Change-Id: I1d9b063d8bdd3d2f0b0f67e6c20eb484ff6a5cc5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Commit 8dec5fcaf8 ("drivers/spi: Add 4-byte address mode flag to
lb_spi_flash") split the existing 32-bit `erase_cmd` field into multiple
fields. The new `flags` field thus created is used to pass information
about whether the flash is in 4-byte address mode.
Unfortunately, we forgot to initialize the new fields in the case that
the flash is not in 4-byte address mode. This means it can have any
arbitrary value, including values where the new flag bit is accidentally
set (causing flash access errors in the payload).
This patch fixes the problem and tries to prevent further issues with
field changes in the future by explicitly zeroing the entire coreboot
table structure before starting to fill in the values.
Change-Id: I3ad9812fc76ae2989dcf4a294034c4e31456c74e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a new Kconfig option, UART_BITBANG_TX_DELAY_MS,
to make the UART TX pin stabilization delay configurable.
A default 5ms (CONFIG_UART_BITBANG_TX_DELAY_MS) delay is added in
uart_init() after the TX pin is set high. This addresses an issue
where the initial character sent by the UART could be corrupted due
to the pin not being stable. The delay ensures the line state is
properly established before data transmission begins.
This was found to resolve early boot console corruption on some boards.
The issue is likely a race condition where the first character starts
transmitting before the GPIO output is fully stabilized.
TEST=Able to build and boot google/zombie w/o any junk characters in
AP firmware log.
w/o this patch:
```
�ɍ���щ�����х�ѥ��b����ٕ��Jrrrjjm UuI5�ፕ�ѥ���������ͥ��х�����jm UuI5���ѥ���ፕ�ѥ��m��jm UuI5����ѕ�ѕፕ�ѥ��m��[DEBUG] NCC Frequency bumped to 1.363(GHz)
```
w/ this patch:
```
[NOTE ] coreboot-25.06-78-gfe786406960e-dirty Fri Aug 01 17:12:22 UTC 2025 aarch64 bootblock starting (log level: 8)...
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] Silver Frequency bumped to 1.5168(GHz)
[DEBUG] L3 Frequency bumped to 1.1904(GHz)
```
Change-Id: I33c9ea65aa42d23acf3b89f977d4985569c144e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88633
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow overriding the default value (true) via devicetree configuration.
If disable_clkstop_sm_support is set in the devicetree,
the corresponding field in alc711_slave is set to false.
BUG=b:417133565, b:420516709
TEST=Verified build and boot with ALC721 and ALC722.
Headphone path switches successfully via audio jack event.
Confirmed SSDT dump at PCI0.HDAS.SNDW.
Package (0x02)
{
"mipi-sdw-simplified-clockstopprepare-sm-supported",
Zero
},
Change-Id: If958cd0c2136e4dd3f60cb9203d9394913d3f66e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88586
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Include the missing header stdbool.h
Fixes compilation error
hybrid_graphics.h:6:28: error: unknown type name 'bool'
while refactoring some code.
Change-Id: I96f7255049cd9e24d74838a173e920a00636b09e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current style is not part of the coding style [1]. The comment has
five lines, so it’s unclear if the short or long multi-line comment
style should be used. Use the short one, to keep it concise.
[1]: Documentation/contributing/coding_style.md
Change-Id: I500340fd02a54c69db4ca5d753fcb690fae1c520
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88491
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Bochs display driver uses port I/O functions to initialize the VGA
device, so it could only have been built on x86 architectures so far,
but its supported devices can be used just fine on others on the QEMU
side as long as the emulated platform supports PCI. A previous commit
adds port I/O functions for more including ARM* and RISC-V, which should
enable this driver to be successfully built and used on these as well.
Allow the Bochs display driver to be built for non-x86 QEMU boards by
changing the Kconfig dependencies. Make VGA text framebuffer support
depend on x86, because it isn't usable at the standard 0xB8000 address
on other architectures. Add a dependency on PCI since this is a PCI
device and vexpress-a9 (qemu-armv7) doesn't have the (emulated) hardware
for PCI.
Change-Id: I7f72d7ea13e54ecf89d067394c02b572c5f92d24
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Due to a flaw in the hardware design, the GL9763e replay timer
frequently times out when ASPM is enabled. As a result, the warning
messages will often appear in the system log when the system accesses
the GL9763e PCI config. Therefore, the replay timer timeout must be
masked.
BUG=b:428025481
Sample output on screen:
PCIe Bus Error: severity=Corrected, type=Data Link Layer
device [17a0:e763] error status/mask=00001000/00002000
[12] Timeout
Change-Id: I6f921f40f169d7811b7bd51145023b549e8aee1c
Signed-off-by: Victor Shih <victorshihgli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88291
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This documents that if the fw_cfg table was improperly configured by
QEMU, the fw_cfg_smbios_init() function would leak memory. We could
add a check to verify that this doesn't happen, but honestly that seems
like overkill. This just documents the issue in case this code is
copied for use elsewhere.
BUG=CIDs 1405799, 1405791, 1405792, 1405796, 1405797
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f253194dae52897633ab5d96bb8c2964b8365d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In order to support runtime evaluation of the TPM base address
introduce and use a new method for CRB TPMs.
Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Adds a new flags field to the lb_spi_flash coreboot table to indicate
if the SPI flash is operating in 4-byte address mode.
This allows payloads to query the current address mode directly from the
coreboot table, preventing redundant checks or re-enforcement of the
mode. The flag is set based on the
CONFIG_SPI_FLASH_FORCE_4_BYTE_ADDR_MODE configuration.
Important: `erase_cmd` was reduced from uint32_t to uint8_t.
Only the least significant byte was ever relevant, so this change
ensures accurate type representation, maintains backward compatibility
with existing coreboot table structures, and frees up space.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I406536432b2a0c7f4108e5b33d5a20c272d917b0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit refactors the logic for entering and exiting 4-byte
addressing mode in the SPI flash driver.
Changes include:
- Renaming SPI_FLASH_EXIT_4BYTE_STAGE to SPI_FIRST_STAGE to better
reflect its broader applicability to initial boot stages.
- Applying SPI_FIRST_STAGE to both the force 4-byte address mode
and exit 4-byte address mode configurations, ensuring these
operations are only attempted during the appropriate early boot
phases.
- Renaming CMD_FORCE_4BYTE_ADDR_MODE to CMD_ENTER_4BYTE_ADDR_MODE for
consistency and clearer semantics, as 0xb7 is typically used to enter
this mode.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I79e2c7bbd222fd0d76072860bdf3feba7e7d587d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Introduces logo_bottom_margin to soc_intel_common_config to allow
adjusting the vertical (or horizontal, based on orientation) offset of
the footer logo from the screen edge. This provides flexibility for
OEM branding placement.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie3942d9eee07091286118ac488d1cc85ecc96c4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Many high-capacity SPI flashes (e.g., >16MB) default to 3-byte
addressing and require a specific command to enter 4-byte address mode.
This commit introduces support for sending the
CMD_FORCE_4BYTE_ADDR_MODE (0xB7) command during flash probing. When
Kconfig option `SPI_FLASH_FORCE_4_BYTE_ADDR_MODE` is enabled, this
ensures the flash chip is immediately switched to 4-byte addressing
after power-on.
This addresses issues with flashes like GigaDevice (GD25LQ128D) and
Winbond (W25Q256JWxx) that mandate this command for proper 4-byte
addressing. The new command definition is in `spi_flash_internal.h`.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I935a0e1d6214d73c8ea487418adc93f016790432
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88156
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the `soc_load_logo_by_coreboot()` function by
extracting common logo rendering logic into a new helper function:
`render_logo_to_framebuffer()`.
The `render_logo_to_framebuffer()` helper is responsible for:
- Loading the BMP image (by type).
- Checking the image size.
- Converting the BMP to GOP BLT format.
- Calculating the appropriate logo coordinates based on vertical
or horizontal alignment, considering panel orientation for the
footer logo.
- Copying the logo data to the framebuffer.
- Releasing the allocated logo buffer.
This refactoring significantly reduces code duplication within
`soc_load_logo_by_coreboot()`, making it more concise and readable.
It also centralizes the logo rendering process, improving
maintainability and simplifying future modifications.
The `soc_load_logo_by_coreboot()` function now focuses on
higher-level orchestration: graphics info initialization, MTRR
setup, panel orientation adjustment, and sequential calls to
`render_logo_to_framebuffer()` for the main and optional footer logos.
Error handling for MTRR and logo rendering failures is streamlined
with a `cleanup` goto label.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat at center of the
screen.
Change-Id: I10f84fd1c2081efcf787d00ab7cfc6bb24feca21
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88032
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
