Originally, there were separate EC firmware builds for the smart
battery (SB) and non-SB versions of the starlite_adl board, but those
have long since been unified. Squash the board variants into a single
board which supports both SB and non-SB boards.
Adjust the board description to reflect that it will support both the
existing N200 and upcoming N355 flavors.
TEST=build/boot starlite_adl on both SB and non-SB boards, verify
battery and all other features function normally.
Change-Id: I2461a094f2455ce333132ffa9f2f83967ae0e927
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a CFR setup menu option to enable/disable the USB micro-SD card
reader, but restrict it to newer boards which use the MXC
accelerometer, as those boards have the card reader on USB2 port 4,
rather than shared with the detachable keyboard on port 3.
TEST=build/boot on starlite_adl boards with and without the MXC
accelerometer, verify only boards with it have the CFR option
to disable the card reader shown, and that the option works
as expected.
Change-Id: I9255d008c6f322d01390ed9f19e4e963cf04eeb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Create the ruby variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:446771934
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_RUBY
2. Run part_id_gen tool without any errors
Change-Id: Ie5f4a152d792f241a0044f18653b5363e1637b49
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89327
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During Uldrenite development, the ISH UART port design and VR settings
were changed, so the switching mechanism was implemented based on the
board ID. Uldrino adopts the latest Uldrenite design; however, its
board ID starts from 0. To resolve this issue, an additional FW_CONFIG
field is added to further distinguish between Uldrenite and Uldrino.
BUG=b:450182476
TEST=Verified the ISH log and used the servod board to dump the CPU
log for checking PMC Descriptor Record 7 at offset 0xC33.
Change-Id: Id24659d6f910de1d3da36c5da808fd768dbdbc37
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89457
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Due to only 1A on DB, the test item of FAFT EC
firmware.DevInsertUSBScreen.insert_usb would be captured much error
message to detect C1 if set the flag.
And then missed to capture the correct message when running the test.
Therefore, removed the DB_1A for pmc_mux on daughter board to fix
the issue.
BUG=b:451436640
TEST=USE="${USE} -project_all project_craaskyu2" emerge-nirva \
coreboot chromeos-zephyr chromeos-bootimage
Confirm firmware.DevInsertUSBScreen.insert_usb PASS.
Change-Id: I6b1a3c99d422c99103818556365b0e5929a18dbf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89538
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Issue=ACP is not active in S3 state and audio playback doesnt work
Fix=Introduce a config option to control this setting.
TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.
Change-Id: Ifbd3e72a4d018e4a14d9459dd3a6804dd27050e4
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89610
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the CS35L56_FAMILY and CS42L43 SoundWire driver configs in
Kconfig to ensure support amp cs35l56 and codec cs42l43 on lapis.
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
{
Device (SW20)
{
Name (_ADR, 0x00023001FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
Device (SW21)
{
Name (_ADR, 0x00023101FA355601) // _ADR: Address
Name (_DDN, "Right Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
BUG=b:444122406
TEST=emerge-fatcat coreboot and dump ssdt.asl
Change-Id: Icab7e38bb5c2733f1bd2a7ddd21b56ace01e64af
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89593
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
CS42L43 contains a range of optional properties which control the
behaviour of jack and accessory detect, and are added here.
These properties are documented in the Linux kernel source code, in the
file:
linux/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml
which contains names, descriptions, valid and default values.
Being optional, these properties will be ignored if not specified.
Change-Id: I53fbed81df9157022384d5879c9d9ed351641ab5
Signed-off-by: Maciej Strozek <mstrozek@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously, only the EDP display path was supported due to incorrect
mutex bitfield assignments and incomplete main path setup logic. This
commit corrects the mutex bitfield assignments after reviewing the
datasheet, and updates the main path setup logic to enable support for
both EDP and DSI display paths, improving overall compatibility.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=Check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: Ic3f901b9dff0a7ec9188212d2311b8394cf5c0e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [Window 1: 1.50GB]
[INFO ] * Base: f0000000, Size: e000000, Tag: 200 [Window 2: 224MB]
kernel before:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window] [PM02: 224MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/swanky with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: Ibb61d3188f75a963e9417685c2808b27055b46d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [Window 1: 1.50GB]
[INFO ] * Base: f0000000, Size: e000000, Tag: 200 [Window 2: 224MB]
kernel before:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window] [PM02: 224MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/edgar with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: I86c38b6f0d3e31affb578dc7a1bf5c8109714bf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Broadwell SoC boards (which use Haswell's northbridge ACPI),
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the dynamically-sized PM02 PCI MMIO window above
MMCONF to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 70000000, Tag: 200 [Window 1: 1.75GB]
[INFO ] * Base: f4000000, Size: a000000, Tag: 200 [Window 2: 160MB]
kernel before:
[mem 0x80000000-0xefffffff window] [PM01: 1.75GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xefffffff window] [PM01: 1.75GB]
[mem 0xf4000000-0xfebfffff window] [PM02: 172MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/lulu with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: I83fa8ca7f9edfd7d185895f8bbff15ee9895d1ff
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configure the GPP_E16 reset line for the touch panel as a GPO.
Configure GPP_E17 to a no-connect by default.
BUG=b:452845001
TEST=`emerge-ocelot coreboot chromeos-bootimage`, flash an ocelotite4es
and verify it can boot to kernel without crashing.
Change-Id: I9ba2009252b84fb85356ef65e7b37017f9d2af43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89630
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the power limit and voltage regulator parameters for
the Panther Lake SoC to align with the recommendations from the Power
Map 2.0 document (#813278). The update addresses discrepancies between
the previous configuration and the optimal settings specified in the
Power Map 2.0 document, ensuring better performance and efficiency.
TEST=Power and Performance team verified that Fatcat devices meet
requirements with these settings.
Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Shaik Sameeruddin <shaik.sameeruddin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89318
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Rather than boards configuring a handful, have common code
configure all relevant ones for the SOC.
Change-Id: I06f202378dd26d99a4fb17f6195dd3fb4df61430
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89525
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This avoids storing the same files in 5 different places in the tree.
Change-Id: I84bd5705613947444f48331d1a2d06b1ab71b2f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Allow mainboard vendors to have common code, controlled by a new
Kconfig option MB_COMMON_CODE.
Change-Id: I5b97b26a70fbbe2e3f659f01aa00b16b76167f88
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89531
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP.
Change-Id: I9b1a272cababc6852b4c2f9c03cc417c1b1d12be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89535
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP.
Change-Id: I203b46320660d326db0cb2733b998003fc12e905
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP.
Change-Id: I09be7910a62441df95b186c8554bc2fe3bf8c92f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Drop the Intel ME-related options since these boards ship with the
ME disabled via HAP. Restrict the power-on-after-fail settings to
the Mini boards since it doesn't really make sense for a laptop.
TEST=build/boot purism librem_mini_v2, verify CFR option functionality.
Change-Id: I0945ad7ddcafc6970a69777ace53d09bb37c749f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit adds a wake configuration to the cnvi_bluetooth device for
all the Fatcat board variants. The "wake" setting is now registered to
"GPE0_PME_B0" using the common CNVi block. This enhancement ensures that
the cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: Id0ef732d45b46a3f59456860d9070fffdab05509
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces changes to the ACPI implementation for the
PTLRVP mainboard by adding power meter support. It defines how the
PAC194x series devices are connected to the I2C controller and details
their configuration. Each device under scope \_SB.PCI0.I2C3 is given
specific methods to indicate its status, resource settings, and device
specific configurations via _DSM. This includes functionality to return
monitored power rail names, resistor values, EMI configurations, sample
frequencies, and Vbus multiplication factors. These changes enhance
the power management capabilities of the mainboard, allowing precise
monitoring and control over various power rails.
BUG=none
TEST=Verify power meter ACPI changes in DSDT.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6e5d38500cac46187283481ef6f84215b14e927b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
As a result of hardware BOM design, U51 (power gate for touchscreen)
would be required to remove on non-touch SKU. The change will cause
the I2C1 touchscreen devices probe ERROR of non-touch SKU since no
power for I2C bus pull-high resistors.The ERROR is waiting I2C stop
condition time out then bootperf test will get fail.
The CL apply fw_config field 19 - PANEL_PWR_SEQ_CTRL for I2C1:
0...disable (non-touch sku)
1...enable (touch sku)
Turn off I2C1 for non-touch sku, and keep I2C1 is on for touch sku.
It will avoid the touchscreen probing error on I2c1.
BUG=b:447513390
TEST=Check boot to kernel time is 1,376 sec under spec and without
I2C probe error in ap log of non-touch sku.
Check touchscreen device works well of touch sku.
Change-Id: I72a68177a90cea88fe283d8499b8378c64206fa2
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
The help description for `CONFIG_BMP_LOGO` in `src/lib/Kconfig` is
updated to be more generic.
Change-Id: Ic95aabe3fa3178ed5a8e4a2105364e8fb397d85f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update Kconfig.name with device/product names where available. Names
were parsed from a ChromeOS Recovery image config file, and matched
to the appropriate board using a script generated by Cursor AI.
Output was spot checked for correctness and compared to other sources.
Development devices were dropped from the results.
Change-Id: I5ac1c153606b7d1f93ea5c72e5ff727bb1f38683
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it. Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.
More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
This was initially tested on Talos II (OpenPower platform) by Raptor
Computing Systems. Later versions were tested using QEMU and ipmi_sim
from OpenIPMI project as well as QEMU's builtin BMC simulator.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67057
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the DPTF parameters as provided by thermal team.
1. Adjust the PSV threshold value of the Passive Policy.
BUG=b:449890912
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team
Change-Id: I8be7da7550994f6a408e2c5bbc6ae4d31fa22ada
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89564
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The hardware is mostly identical to the well supported Thinkpad T480
aside from some swapped PCIe clock lines. Consequently, coreboot will
boot to the OS in combination with a properly deguarded Intel ME.
The VBT was obtained from the latest stock BIOS (1.43, N27ET57W) with
intelvbttool. GPIO assignments have been cross-checked against publicly
available schematics (Tachi-2).
The patches have been validated on a Thinkpad T580 P/N 20L9-001NUS. With
SeaBIOS rel-1.17.0-4 as payload, the system boots into Linux (debian 13)
and Windows 10 22H2 with the hardware working as expected.
Change-Id: Iaa8368aeda11560bc0c1c77e7611ed9879d038da
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89499
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MAINTAINERS file is used to automatically assign reviewers on
Gerrit, however as the paths are not checked they can become out of
sync with the codebase. This is detrimental to both the uploader
and the maintainers, as the change may not get the appropriate
attention.
Fix this problem by adding a simple check for 'F' and 'X' entries.
Change-Id: I7755f6317edda0d8d976e138cfafcc3ef5850ead
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Issue=ACP is not running in S3 because the XTAL FCH CLK is turned off.
ACP needs to be running in S3 for one of our customers who needs audio
playback to work in S3.
Fix=Introduce a config option to control this setting.
TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.
Change-Id: Ie9c0e96f87050b542a1ddf3f59d6b67064ac8faf
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Both of these boards have 20Gbps TBT2 ports, capable of accessing
PCIe labels from the PCH. Therefore, select
SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.
Change-Id: I4528f2748d1fa3988296f695dac045de536c43df
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The second port was set to 07.0, which is the first port. Correct
this.
Change-Id: I8d1a046ea863beb921c103cb2aa82b09d75f2be7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set pads that are not used to PAD_NC
Change-Id: I1a50bc8eab9d086b71cc33f56789bdd10f133864
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It seems that FSP was fixing up the TBT0 TXD and RXD GPIOs;
add the missing GPIO configuration and group them.
Change-Id: I22af542fe008395a47c64396f481442ff3bcc9a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89584
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Emply the standard Star Labs format for the config straps; this is
a non-functional change - just easier to read.
Change-Id: I04c7a8046c21577154593996866448fc4c05d03b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set pads that are not used to PAD_NC.
Change-Id: I3bf005b743fdcaf75c456c59354e7440ec0faefb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89581
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Apply the standard format for configuring the config straps. The
configuration of the straps isn't changed, just written more clearly.
Change-Id: I2cf130fbf7572a4014e97c14885951e5f604cfa8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89578
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Non-functional change that makes it easier to see what is actually
configured.
Change-Id: I2ffb11ef73a0b2c9e5236b2edb9ec187a045374c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add framebuffer region to reserve 24MB for the boot logo feature.
BUG=b:319511268
TEST=The logo is shown in the ramstage.
Change-Id: I183651f7bd28de5551a15bd335bc2eed5f0804eb
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The RW_A and RW_B firmware sections are increased by 256KB, from 1500K
to 1756K, to support larger firmware images. With bootsplash enabled,
the remaining space in these sections is approximately 15KB, which is
insufficient to hold the bootsplash assets. This increase provides the
necessary space. Additionally, with more features anticipated from the
payload (depthcharge), this extra space serves as a reserve to prevent
future build failures due to insufficient space.
The RW_LEGACY section is also adjusted to fill the remaining space.
WARNING: Please do NOT cherry-pick to rauru firmware branch.
BUG=b:450510630,b:319511268
TEST=emerge-rauru coreboot chromeos-bootimage (with BMP_LOGO enabled)
Change-Id: I70aaa9e7011b7f2376b7bc28caac27c0a86aa20a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change introduces support for displaying a bootsplash logo during
boot on Mediatek platforms.
A new `display_logo` function is added to render a logo from the CBFS
into the framebuffer. This function is called from `mtk_display_init` if
`BMP_LOGO` is enabled in the board's Kconfig.
Additionally, this change refactors the backlight configuration logic
into a new `panel_configure_backlight` helper function for better
clarity.
BUG=b:319511268
TEST=Verified on Hylia that the bootsplash logo is displayed correctly
during ramstage. Boot time increased by 562ms due to display
initialization.
Change-Id: Ibcfaa7d309eb4a0b14244b98c78a0dc32e6836e5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89543
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To save memory, only allocate and configure the framebuffer when display
output is required during boot.
This is achieved by:
1. Making the `framebuffer` memory region optional.
2. Guarding the framebuffer's uncached MMU configuration with a
`display_init_required()` check.
This ensures the framebuffer is prepared only when needed, saving
memory on boot paths that do not require display.
BUG=b:319511268
BRANCH=none
TEST=emerge-rauru coreboot
Change-Id: I3808031160e421de7c21f585f4b79d42bfddccc4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reserve DDR region for HYP, QTEE SMMU buffers, Gunyah and ACDB. The
carveout is located at: 0xFF800000 - ((n*5.5)+1+32+3), where n is
the DRAM size. This region is protected by QTEE and must remain
reserved to prevent access by other components.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified carveout region reservation via depthcharge serial log.
Prior to reservation, the memory wipeout range was [0x000000f61f7920,
0x000000ff800000). After reserving the carveout, the range is reduced
to [0x000000f61f7920, 0x000000f7c00000).
```
Wipe memory regions:
[0x00000080000000, 0x00000080a00000)
[0x000000815a0000, 0x00000081a00000)
[0x00000081cf4000, 0x00000081e00000)
[0x00000082800000, 0x00000085380000)
[0x00000085f80000, 0x000000866c0000)
[0x00000091380000, 0x000000c72c4000)
[0x000000c7800000, 0x000000d8000000)
[0x000000d9600000, 0x000000f1000000)
[0x000000f61f7920, 0x000000f7c00000)
[0x00000880000000, 0x00000c00000000)
```
Change-Id: I511452054dcf10f8a2254eafb2f127c05a3249e5
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89552
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
