Add Measured Boot that is specific to Apollolake, and is used
for measuring the IBBL, IBB and TXE. The IBB is measured only if it
exists, and only after it has been loaded into the CSE.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I61ce4a34875d6d3357d4088167cdd887bafdff23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65272
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Copy the IBB into CAR via the CSEs RBP to ensure it has not been
modified.
Test on the StarLite Mk III and Mk IV:
Without VBOOT:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: IBB Size : 88
With VBOOT:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: IBB Size : 102
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0d4e26834cef4c876e37e414b424a031c11111ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a loader that will load the IBB into the CSE via the Ring Protocol
Buffer.
All registers were taken from Intel document number #336561.
Change-Id: Ia41e3909f8099d2ea864166e9ea03e10e40a1b68
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot's method of creating IFWI is to modify an existing IFWI
images by deleting the IBB, replacing the IBBL with the bootblock
and everything else is put in the OBB.
This poses a problem when using Intel's FIT or technologies such
as Boot Guard. The main problem is that the IBB is never verified by
the CSE or copied from SRAM to CAR, so the CSE cannot complete BUP
and stays in recovery mode. The vast majority of the stages in
Apollolake's Secure Boot flow is not met using this method (Intel
document number 597827 summarizes these steps).
This patch series is based on the principles of a patch from Brenton
Dong (CB:17064) creates an IBBL, IBB and OBB binaries with the
correct functions to complete the Secure Boot flow. This is to copy
the IBB from SRAM using the CSE's Ring Buffer Protocol.
These binaries can then be used by FIT or coreboot's existing
method of hacking IFWI together (IFWI_STITCH) via IFWITOOL. If it is
the latter and Boot Guard is enabled, the hashes for IFWI and "ibb+obb"
must be recreated.
Whilst this option doesn't form a complete image, the components it
builds will work as Intel intended them to once stitched correctly into
an IFWI image.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This updates FSP UPDs for PCH PM SLP minimum assertion width and reset
power cycle duration to reduce the delays during a global reset and S5
suspend and resume flow.
Reference:
Panther Lake External Design Specification (EDS) Volume 2 (#813032)
BUG=None
TEST=Build a fatcat coreboot and issue a global reset to check the reset
delay is reduced to 1 second. Issue a lid close to suspend to S5 and
wake up by lid open to check the delay is reduced to 1 second.
Change-Id: If94917879125b1a523de131936047b497cce8ba7
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88444
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This configures FSP UPDs for PCH PM minimum assertion widths and
reset power cycle duration per mainboard variants configuration.
This also checks the reset power cycle duration is not be smaller
than SLP_S3, SLP_S4 and SLP_A Minimum Assertion Width.
PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
The Reset Power Cycle Duration starts at 20ms and increases by 20ms
for each step, beginning from 0x0 to 0xFF. Each subsequent increment
corresponds to an additional 20 milliseconds in duration.
Reference:
Panther Lake External Design Specification (EDS) Volume 2 (#813032)
BUG=None
TEST=Build a fatcat coreboot and boot to OS without an issue.
Change-Id: I7234c7539c1e7eb5e2b8c04ccff6c62c853d6807
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88443
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Due to a flaw in the hardware design, the GL9763e replay timer
frequently times out when ASPM is enabled. As a result, the warning
messages will often appear in the system log when the system accesses
the GL9763e PCI config. Therefore, the replay timer timeout must be
masked.
BUG=b:428025481
Sample output on screen:
PCIe Bus Error: severity=Corrected, type=Data Link Layer
device [17a0:e763] error status/mask=00001000/00002000
[12] Timeout
Change-Id: I6f921f40f169d7811b7bd51145023b549e8aee1c
Signed-off-by: Victor Shih <victorshihgli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88291
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation for adding additional GM45/ICH9 based Dell Latitude
laptops, rework the E6400 port to use a variant scheme so that code can
be shared.
Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This adds changes to conditionally enable the config
`DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` when
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` is enabled.
This ensures that MIPI firmware and drivers are compatible with
Panther Lake pre-production silicon.
BUG=b:424355826
TEST=Ensures `DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC` is
enabled for google/fatcat4es and all variants with ES silicon.
Change-Id: I9687618cfceac32425fa19b4f1f30040b88a2d15
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88220
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This updates the Kconfig for Google Fatcat mainboards to include
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` option to ensure
compatibility with Panther Lake pre-production silicon. This selection
aligns these boards with the necessary pre-production silicon settings
BUG=b:424355826
TEST=Ensure mainboards like fatcat4es and fatcatnuvo4es have
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` config enabled.
Change-Id: Icde96976e0e3ccfc543bc948d2923e0f84e7da68
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88219
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default, when building all boards, we use a single thread for each
board and build a number of boards in parallel. The --sequential-boards
flag will change that to use all specified cores to build each board
in sequence.
This can give better performance in some cases where multiple builds
are conflicting for a given resource.
Change-Id: I35ae7a5df5de48b8ce3373b6659be0df5104ed39
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88239
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's no longer maintained here other than to address specific issues,
and it prevents us from benefiting from upstream changes. Already,
switching to the GCC toolchain saves 5-10 KiB.
Use the GCC toolchain over the backwards-compatible GCC5 one, since the
latter is being deprecated, and the former landed a few years ago,
in edk2-stable202305.
Change-Id: I47e47592ea29f5a09790b284378f28385faf29f9
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88429
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows EDK2 build files to decide whether these modules should be
built.
Change-Id: I12dc346d17ab0f963dedd5560b66b96210a4ec48
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This patch introduces a new configuration option
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` that allows users to
specify if their mainboard is using Panther Lake pre-production silicon
aka Engineering Silicon (ES) with pre-production signed ME Firmwares.
The default value is set to 'n', ensuring it is disabled unless
explicitly chosen.
BUG=b:424355826
TEST=No change in the functionality, just added new configs.
Change-Id: I8ad83b07f057a227b62e33b6c6c0f46c3952be6b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88218
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to Pujjoquince does not have ISH, thus define bit 29 in
firmware_config to indicate ISH presence per platform.
BUG=b:417599885
BRANCH=none
TEST= Use the command ls /dev/cros_ and no cros_ish option
will appear
Change-Id: I286300eadf7991d3a30936f5904ff3eef4480039
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88364
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add HYNIX H54G46CYRBX267 as id 0, and add HYNIX H54G56CYRBX247
as id 1, resulting in the list below:
DRAM Part Name ID to assign
K4U6E3S4AB-MGCL 0 (0000)
K4UBE3D4AB-MGCL 1 (0001)
MT53E1G32D2NP-046 WT:B 1 (0001)
NT6AP512T32BL-J1 2 (0010)
NT6AP1024F32BL-J1 3 (0011)
CXDB4CBAM-ML-A 2 (0010)
H54G56CYRBX247 1 (0001)
H54G46CYRBX267 0 (0000)
BUG=430792154
TEST=Use part_id_gen to generate related settings
Change-Id: I6ea840862b4b7b728a351425da9fc4052c201e3c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88419
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far back as the x201, Lenovo's EC ACPI has treated 128 as an invalid
value, and returned a corrected value when it is reported/read from EC
RAM. Drop the ME workaround, which most H8-equipped boards select, in
favor of Lenovo's logic, since both accomplish the same result.
Change-Id: Icdc91e439ec30c8263de5810a13e75f7595472a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88416
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looking at the ACPI dumps of many older Thinkpads, most do not have a
second thermal zone (zone 1), they only use zone 0. This doesn't seem
to be a problem for most boards in the tree currently, but newer boards
(such as the T480) are reporting critical temperature errors on zone 1,
due to differences in the EC RAM layout (ie, TMP1 is not valid).
To mitigate this issue with the T480 (and likely other newer boards),
only include the ACPI code for thermal zone 1 for boards which need it.
Explicitly select it for those boards based on ACPI dump analysis and
model similarity.
Change-Id: Ic022f2e14b2cae74656c0ac85ba8410d50cdc9de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Using Kconfig options instead of chip registers allows for newer boards
which do not implement BT/WWAN detection to not compile in the GPIO-
related parts, which are only valid for older (pre-FSP) platforms.
Change-Id: Ibfe738adfc75abfaf078c6b7ff5472a1424909f5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88414
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot lenovo/t480 w/edk2 payload
Change-Id: I8f5c335a8b9d1697b77b3c3542bd96f98583dbf6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot lenovo/t480 w/edk2 payload
Change-Id: I198f569e69abd42071df4d5354cd2bb258749257
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88393
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the caboc variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:420796212
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_CABOC.
Change-Id: I424933574873defe5289fbe7309270583cb8a49e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88379
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces Direct Memory Access (DMA) support for the Intel
Fast SPI block, enhancing data transfer capabilities from SPI flash
memory. The primary motivation for this addition is to improve
performance in multitasking environments by offloading read operations
to DMA, thus freeing up CPU resources for other tasks. The traditional
memory-mapped SPI flash read operations can be CPU-intensive and slow in
scenarios where large data volumes are transferred.
This feature is gated by a FAST_SPI_DMA configuration option. The DMA
operations are integrated with existing SPI flash read functionalities,
ensuring fallback to memory-mapped operations if DMA is unsupported or
fails. The DMA code implementation uses mutex-based synchronization to
ensure thread-safe DMA transactions.
The boot_device_ro() function has been modified to check for DMA support
and installs custom DMA operations when available.
We conducted measurements on a 200 KB data transfer and noticed a 1.8%
improvement with DMA compared to memcpy on memory-mapped SPINOR, with
DMA taking 10.8 ms and memcpy taking 11 ms.
Change-Id: I4b4ca9ff08e436ca627afa6b0d9bb00f3c450a5e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88277
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the memory layout for AP Firmware boot on the
Qualcomm x1p42100 SoC. This update is crucial to ensure that all
processors and co-processors can successfully load their
respective blobs during the process of booting to the OS.
TEST=Successfully booted google/blueu.
Change-Id: Ibce385e9d201f0a3c5daf19e8dfe235fa9f695af
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit extends the cooperative multitasking functionality to
support the x86_64 architecture. Previously, cooperative multitasking
was only available for x86_32, as indicated by the error directive in
thread.c.
A new thread_switch_64.S file has been added to implement 64-bit
register handling for thread switching, and thread_switch.S has been
renamed to thread_switch_32.S accordingly.
Change-Id: I14ed625160a62e42d800757d30397c6c85f943b4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88216
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change incorporates the final statistics for the 26.06 release and
changes it from upcoming to the final version of the notes.
- Add a section for Project Updates
- Update the introduction, removing the comment about GCC 15, which was
a bit confusing. We can now build the toolchain with GCC 15, but it is
not yet part of the toolchain.
Change-Id: I27defefacdf8b3a826c801da051e3218394f81e2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88312
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable USB3 WWAN since the issue is fixed with the latest schematics.
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:424945817
BRANCH=none
TEST=Remove Verify USB3 WWAN with the latest schematics.check the WWAN USB3 interface is now working properly..
Change-Id: I30eb74a8456bc63c964269822e0b10135d24aa1f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:424945817
BRANCH=none
TEST=Verify USB3 WWAN with the latest schematics.
Change-Id: I30eb74a8456bc63c964269822e0b10135d24aa1f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88340
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because of intel suggestion, the change will fix the sensor driver
could be "probe fail" issue. So update mipi camera parameters' value.
Change:
1. CSI Camera lanes from 2 to 4.
2. Value of index 0 of frequency link array from 720000000 to 360000000
3. Value of index 1 of frequency link array from 360000000 to 180000000
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check mipi camera function.
Change-Id: Ieea6d99182df9c5aa9ca7a7f72f031921c24199e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Update fingerprint enable pin status to keep the module disabled
and in reset in firmware. This allows the module to be enabled
and released from reset during kernel boot via ACPI.
BUG=b:411558536
BRANCH=none
TEST= Boot to OS and into VT2, use ectool --name=cros_fp version
will return fingerprint version information and check the
functionality works.
Change-Id: I98707e0e6ba550f6b7d75a84e72843c3873fa56c
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:430467732
TEST=emerge-nissa coreboot and elan touchscreen can work well.
Change-Id: I08a32eae272d5ef93f1c89bcb96b9ba50c037624
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The PS/2 Keyboard and Mouse won't work in Microsoft Windows 10 or 11 on
these tested HP variants:
- compaq_pro_6300
- compaq_8200_elite_sff
- compaq_8300_elite_sff
Unless the following line to acpi/superio.asl was added:
#include <drivers/pc80/pc/ps2_controller.asl>
Without this patch PS/2 ports only work in EDK2, SeaBIOS, GRUB 2 and
Linux.
Dmesg output for comparison without and with patch (trimmed):
[ 0.232601] pnp: PnP ACPI: found 16 devices
...
[ 0.231146] pnp: PnP ACPI: found 18 devices
...
TEST=Boot Windows 10 / 11 verify that PS/2 Keyboard & Mouse works!
Although only 3 models were tested and this common option affects all
snb_ivb_desktops variants I'm pretty confident it will work on all the
others since it also works on boards from other Manufacturers from Dell
and GIGABYTE even single port with splitter cable.
Change-Id: I21c10cc24c25887ab822a5889de5eec3b3537ac9
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88322
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The boot time is improved by 50ms in bootblock.
BUG=b:379008996
BRANCH=none
TEST=check the boot time by `cbmem`.
(previous)
11:start of bootblock 247,551 (60)
12:end of bootblock 312,495 (64,944)
(now)
11:start of bootblock 255,424 (60)
12:end of bootblock 270,911 (15,487)
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I0c3a5cff7eecb67e34d8ff1d3084f6a34d9cdbe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88368
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This HP desktop comes in 4 different CPU variants. This port was made
using the Pentium 3558U @ 1.70GHz variant with 2*4GB DDR3L SODIMM RAM
modules with a single SATA adapter cable. Other variants may come with
an M2.SSD slot which may need other devicetree.cb PCIe / SATA edits!
Model: HP 260 G1 DM Business PC
Regulatory Model: TPC-1011-DM
Product No.: N9F00EA#ABH, 260G1eD/G3558U/500h/4X/50f NL
Mainboard: E131920, 791401-002
Pure autoport (initial commit) doesn't boot, further patches bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, (m)PCIe fixes enabling onboard LAN and mini PCIe slot
and some NPCD379 code from other HP desktops make most superio related
functions work for this PC.
Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L6406E in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!
Tested:
- coreboot 25.06-77-g812d0e2f626d as base
- EDK2 (MrChromebox/2502)
- SeaBIOS 1.16.3
- SystemAgent mrc.bin (haswell/peppy)
- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
- DP / DP++ (HDMI) & VGA all available during POST, BOOT and OS
- Pentium 3558U
- RAM single 4GB and dual slot 8GB total with 1.35V DDR3L SODIMMS
4GB DDR3-1600 - SK Hynix HMT451S6BFR8A-PB (2016-W01)
HMT451S6BFR8A-PB NO AA 1601
1Rx8 PC3L-12800S-11-13-B4
4GB DDR3 1600 - Kingston 9905469-143.A00LF (2016-W05)
KTH-X3CL/4G
1.35V
BPMK0831621
9905469-143.A00LF
0000007258426-PW005291
- Fedora MATE 42 (Kernel 6.14)
- KDE NEON 6.4 (Kernel 6.11)
- Audio Outputs HDMI, Headphone, Lineout & Speaker (left&right chan.)
- USB2/3 all ports
- Realtek onboard Gb LAN
- miniPCIe slot + its embedded USB (Intel Wireless AC3160HMW+BT)
- SATA port using the original flatcable adapter
- PowerButton (Poweron/Poweroff/Wake)
- LEDs HDD & POWER (both off during suspend)
- Shutdown/Reboot/Suspend
- Strip down the Intel ME/TXE firmware (make menuconfig)
- Disabling ME HECI (manually disable in devicetree.cb)
- flashrom -p internal -c "MX25L6406E/MX25L6408E" (read & write)
Not tested:
- Broadwell mrc.bin
- Front Microphone Port
- USBDEBUG
- VBIOS
Not working:
- FAN control its either full OFF or full ON see instruction!
- Wake on LAN
- Ethernet is detected as PCIe slot connected instead of onboard
- Disable Intel ME PCI interface (make menuconfig)
- Windows 10/11 USB detection/hotplug issues (all USB ports)
- Haswell NRI (posts & boots but will shutdown in less than a minute)
FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!
The data.vbt blob was extracted using debugfs from the OEM firmware
v2.19 which enables all video outputs Displayport / DP++ (HDMI) and VGA.
Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.
Change-Id: Ifedd9f700e5f3875d3577fa56225d9d49d622b47
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88326
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update TPM related default value for TPM_TIS_ACPI_INTERRUPT based on
schematic_1433518 after mapping GPP_B to GPE0_DW1.
BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I890c6779a24eaa7804594003466e8660af4becc2
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88358
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch updates the GPE configuration for Ocelot in baseboard
devicetree based on schematic_1433518.
BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I60bcf586ab8653732925bfd9393baef226519c3a
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88106
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, the touchscreen IRQ pin was not correctly configured to
GPP_F18_IRQ, which caused an unexpected interrupt storm and led to
the touchscreen becoming unresponsive. This change sets it to the
correct configuration. (schematics version 20250611_v31)
BUG=b:430200649
TEST= Ensure the touchscreen is working properly.
Ensure the interrupt count increases only when the screen is touched
via 'cat /proc/interrupts | grep ELAN'
Change-Id: I20cc9632df76acdfafd2968ece0dde8ee95cc791
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When battery is not present, reduce power limits to below 45W,avoid
inability to enter the system.
To avoid poor efficiency of the adapter, leave a margin and set the
powerlimit to 38W.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:418695656
BRANCH=None
TEST=
1、built (emerge-nissa coreboot chromeos-bootimage) and push ap firmware
to dut.
2、Connect 15W machine without battery to 45W adapter and check if it
starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38
watts.
Log result:[INFO] CPU PL4 = 38 Watts
Change-Id: Iadd43c75ea9235b7ba0e3b97ef460280c13ef1e3
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Because of internal misunderstanding, modify mipi camera FW_CONFIG
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
fw_config.
Change-Id: Id2d62d14bdfd6ad925c5a0c1a9799350a93e57e2
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88352
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Align USB3 Type-A and the related GPIO settings with Pujjolo schematic
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).
BUG=b:427962702
TEST= Connect USB 3.0 devices to the Type-A interface and use "lsusb -t"
command to verify the connection
Change-Id: I559dc8105258b91ca89b2f10644e4f95d6a4a085
Signed-off-by: Ben Kao <ben.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88290
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit enhances the Kinmen variant of the Fatcat mainboard by
introducing an `fw_config` field for AUDIO. This field includes an
`AUDIO_UNKNOWN` option, providing a clear state when no specific audio
configuration is selected or known.
Furthermore, a probe statement for `AUDIO_ALC721_SNDW` has been added
to the `hda` device. This ensures that the system can correctly identify
and initialize the Realtek ALC721 audio codec when present.
These changes improve the flexibility and accuracy of audio
configuration and detection for the Kinmen board.
BUG=b:430205874
TEST=Able to boot google/kinmen to UI without valid Audio configuration.
Change-Id: I86634a4a49c4006584fc808719b2891186953a51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88367
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an `AUDIO_UNKNOWN` option to the `fw_config` for
the Francka variant of the Fatcat mainboard. This allows for a default
or fallback state when a specific audio configuration isn't known or
desired.
Additionally, this change introduces audio probe statements that allow
the system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.
BUG=b:430205874
TEST=Able to boot google/francka to UI without valid Audio
configuration.
Change-Id: I34f7fe5f0509cbddfd3648afb087786373fcf8df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
