erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/fatcat: Update PCH reset power cycle duration to 1 second

Browse source 
This updates FSP UPDs for PCH PM SLP minimum assertion width and reset
power cycle duration to reduce the delays during a global reset and S5
suspend and resume flow.

Reference:
 Panther Lake External Design Specification (EDS) Volume 2 (#813032)

BUG=None
TEST=Build a fatcat coreboot and issue a global reset to check the reset
delay is reduced to 1 second. Issue a lid close to suspend to S5 and
wake up by lid open to check the delay is reduced to 1 second.

Change-Id: If94917879125b1a523de131936047b497cce8ba7
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88444
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jamie Ryu 2025-07-15 17:55:44 -07:00 • committed by Matt DeVillier
commit 61b4e1983c
1 changed files with 7 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
View file

@ -62,6 +62,13 @@ chip soc/intel/pantherlake
# Enable Energy Reporting
register "pch_pm_energy_report_enable" = "true"
# PCH PM SLP miminum assertion width and Reset Power Cycle Duration
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S"
# As per document 813278, the following PTL SoC supports Fast
# V-Mode (FVM) on cores (IA), Graphics (GT), and System Agent
# (SA). The ICC Limit is represented in 1/4 A increments,