The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on dewatt, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I3eeae7b453589a2253226709dd6cfcff1862ea17
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Set SYSTEM_TYPE_CONVERTIBLE for Zork-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI.
Change-Id: I53ce5222e6b6984ef6e3b3c89ecfbae7620aaf36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Set SYSTEM_TYPE_CONVERTIBLE for Kahlee-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI.
Change-Id: I63d815f4cf46aee064db4a23b97c399aa334aad0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91749
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for the Dewatt variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.
Change-Id: I01bd8a4255b2cacc01e9eda703e88af57c8f58c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.
TEST=build/boot Win11 on frostflow
Change-Id: I2ced532443e60e9cbb4e482feceab175aed9a155
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91795
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change touchpad and touchscreen IRQ from edge to level triggering across
all skyrim variants. Required for Windows driver compatibility.
TEST=build/boot Win11 on frostflow; verify touchpad/screen functional.
Change-Id: Ibbc275112536b4d555b127271ee264414d06c5cb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91794
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.
TEST=build/boot Win11 on dewatt
Change-Id: I04593166aad8d3c2c601ba489237a5f45be95fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91793
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ACPI_GPIO_IRQ_LEVEL_LOW instead of EDGE_LOW for Elan touchpads.
Required for Windows driver compatibility.
TEST=build/boot Win11/Linux on dewatt; verify touchpad functional.
Change-Id: I712134860eee456c2c103c2ca8543020c58027f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91792
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO for the proximity sensor, which is only used by ChromeOS for
WiFi power/SAR purposes, causes an IRQ storm under Windows. Only
configure it when building for ChromeOS.
TEST=build/boot Win11 on vilboz
Change-Id: I38955f2e11c7eb412416884b4769e70dd1bde6de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Windows ACPI rejects devices that use both GpioInt in _CRS and a GPE in
_PRW (BSOD 0x1000D). Switch touchpad and fingerprint reader to
ACPI_GPIO_IRQ_*_WAKE so wake is expressed via GpioInt SharedAndWake
instead of a separate _PRW GPE, keeping wake support while staying
Windows-compliant.
TEST=build/boot Win11 on morphius
Change-Id: I2a47b8435fb19ec39d19e09967defa91ae58a85b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91790
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change Raydium and ELAN touchscreen IRQ from edge to level triggering
across berknip, dalboz, ezkinil, trembyle, and vilboz variants.
Necessary for Windows driver compatibility.
TEST=build/boot Win11/Linux on ezkinil; verify touchscreen functional.
Change-Id: I126589f9412f405d69961919bf61c4c60f623676
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit introduces initial support for PCI Express on the
Qualcomm Calypso SoC.
Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
platform will not use the standard MMCONFIG ECAM for PCI
configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
is enabled, incorporating common PCIe helper functions.
BUG=b:496650089
TEST=Able to build google/calypso.
Change-Id: I813e0811e9fd5b6ceefbf72635998a26536987c8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the sku_id() function for the Mensa mainboard to replace
the existing placeholder.
The SKU ID is retrieved from the Chrome EC using the common
google_chromeec_get_board_sku() interface. To optimize performance and
avoid redundant SPI transactions to the EC, the value is cached
after the initial read.
BUG=b:496650089
TEST=Build and boot on Mensa; verify SKU ID is correctly reported in
cbmem logs.
Change-Id: Ibaef20913e8043a02b2468d1157ac1a4a2087fc6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit adds the `clock_init()` function for the Qualcomm calypso
SoC. This function is now called at the beginning of
`bootblock_soc_init()` to enable SoC-specific clock setup early in the
boot process.
The `clock_init()` function definition is currently a placeholder
and will be populated with the required clock configurations in
subsequent changes.
BUG=b:496650089
TEST=Able to build google/mensa.
Change-Id: I3886670348e998b3d80d33643e2256af4eb47fd7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The bootblock requires early initialization of the Quad-SPI (QSPI)
controller to enable reading firmware from flash memory.
This commit adds calls to `quadspi_init()` with a 75 MHz bus clock
and `qupv3_fw_init()` within `bootblock_soc_init()`. This ensures
that the essential hardware for flash access and related QUPv3
functions are properly configured during the boot process.
BUG=b:496650089
TEST=Able to build google/mensa.
Change-Id: I225485cf601c62b1ba695eb61f786a1360790f41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91903
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the default Kconfig values for the google/mensa mainboard
to specify the correct hardware instances/buses used for various
peripherals as per mensa schematics (dated 03/10).
Changes:
- TPM I2C bus set to 0x01.
- ChromeEC SPI bus set to 0x16.
Removes previous TODO placeholders.
BUG=b:496650089
TEST=Successfully built google/mensa.
Change-Id: Ic377be3dc165bf1c1e19031994d87ea45d6c2dc0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds QUP-SE entries as applicable for the Qualcomm Calypso
SoC.
This includes:
- Add new entries for QUPV3_3 SEs.
- Update base addresses for all QUP-SEs.
- Base GPIO pin function assignments.
- Definition and GPIO mapping for relevant QUP Serial Engines (SEs).
- GPIO mapping for the QSPI interface.
Additionally, update GPIO PINS for QSPI and UART.
BUG=b:496650089
TEST=Successfully built google/mensa.
Change-Id: Iab0eecc08d11d99d2534010af86217e6cc2a1961
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update the default Kconfig values for the `soc/qualcomm/calypso`
to specify the correct hardware instances/buses used for various
peripherals as per datasheet for mensa (dated 03/10).
Changes:
- Boot SPI flash bus set to 26.
- Console UART instance set to 21.
Additionally, remove previous used TODO placeholders.
BUG=b:496650089
TEST=Successfully built google/mensa.
Change-Id: I89a298b13eb7761f1767d054c09eafdb3daf0927
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces basic support for the google/mensa mainboard,
based on the Qualcomm Calypso SoC.
Changes:
- Add placeholder mainboard callbacks to enable control flow from /lib
and Qualcomm SoC code.
- Populate the bluey mainboard directory with a copy of the bluey
codebase, removing SoC/mainboard-specific implementations.
This provides a minimal working build for google/mensa, allowing
upstream builders to compile the mainboard. This facilitates easier
verification of subsequent changes.
BUG=b:4966500890
TEST=Successfully built google/mensa with Qualcomm Calypso SoC.
Change-Id: Id30a766c1bc6b37a6d35ba933c207951ab83f4d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces a basic SoC framework for the Qualcomm
Calypso SoC enabling initial build integration.
Key changes:
- Add placeholder SoC callbacks to facilitate control flow from /lib
and Qualcomm common code.
- Populate the calypso SoC directory with a copy of the X1P42100
codebase, with SoC-specific implementations removed.
This provides a foundational structure for Calypso development
within the `soc/qualcomm/calypso` directory, ensuring the upstream
builder can successfully compile the SoC code.
This allows for incremental development and integration.
Reference Document: Calypso Hardware Register Description
BUG=b:496650089
TEST=Successfully built google/mensa with the Qualcomm Calypso SoC.
Change-Id: Iabbbf26c9e08906db2be024911061837fdf83bd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91892
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The X1P42100 SoC and future Qualcomm platforms support more than two
QUPV3 wrappers. This patch extends the common Qualcomm drivers to
handle a third wrapper (QUP_WRAP3).
Details:
- clock.c: Update clock_configure_dfsr_table() to support wrap3.
- qupv3_config.c: Initialize the third wrapper if defined.
- addressmap.h: Add QUP_WRAP3_BASE defines for sc7180, sc7280,
and x1p42100 (defaulting to 0 for older chips).
Change-Id: I58ed310c65319f26ec029071d170237130d9ba19
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The generic config name SOC_QUALCOMM_BASE is too broad and could
potentially conflict with other Qualcomm SoC families or common
code.
Rename it to SOC_QUALCOMM_X1P42100_BASE in both Kconfig and
Makefile.mk to ensure the configuration is explicitly scoped to
the X1P42100 series.
Change-Id: Idb74ad5ecd6180e3b472a5d007157fcc76f3e89d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91891
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, display_startup() is called unconditionally during
mainboard_init(). For normal boot paths, this can lead to unnecessary
latency (40ms) issues.
Modify the initialization flow to:
1. Initialize display early only for low-battery or off-mode
charging paths to ensure the user sees the charging UI.
2. Defer display initialization for all other modes to a new
mainboard_late_init() function.
3. Use a static flag (display_init_done) to ensure display_startup()
is only executed once regardless of the entry point.
TEST=Verified bluey still shows charging animation when low on
battery and boots to OS normally. Able to save 40ms of the boot time.
Change-Id: Id6bdda90b7f67c13cd7334ba17131a8243af0cdb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91845
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The URL must have the .pdf extension now, otherwise gets a 404.
Add a note on later revisions of Sure Start.
Change-Id: I00ab30b461795c672890a21d1fb2af929865c822
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Khalifa Rouis <khalifa@missingno.tech>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Default-enable CONFIG_TCG_OPAL_S3_UNLOCK for Star Labs boards so NVMe
OPAL devices can be unlocked via SMM on S3 resume when the payload
provides the password for the current sleep cycle.
TEST=build/boot adl/hz and starfighter/mtl with TCG enabled, suspend,
and verify SSD can be read after resume.
Change-Id: Ic3d9611295b1bdf9ea49cd6d4d6c924f8eafd746
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91046
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OPAL S3 unlock may run before an RTD3 NVMe is powered on. When the
storage root port uses the RTD3 ACPI driver, trigger the OPAL unlock SMI
at the end of _ON once the port has powered the device.
Do not rely on _ON being invoked during S3 resume. Always trigger a
best-effort unlock during the coreboot resume path. If the NVMe init
path fails (rc=1), keep the sleep cycle armed so a later trigger (e.g.
RTD3 _ON) can retry the unlock.
TEST=tested with rest of patch train
Change-Id: If83b59973ad878c31e19d146fec8bdbb6406ec2f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91416
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide common entry points for the OPAL S3 unlock feature and wire them
into the generic x86 SMM and S3 resume code.
- Add opal_s3_smi_{apmc,sleep,sleep_finalize} helpers.
- Call these helpers from the default weak mainboard SMI hooks when
CONFIG(TCG_OPAL_S3_UNLOCK) is enabled. This keeps the feature usable
without forcing boards to implement new SMI handlers.
- Trigger the SMM unlock on S3 resume from arch/x86/acpi_s3.c.
Select SMM_OPAL_S3_STATE_SMRAM so the secret is persisted across SMM
handler reload. Add a delay and retry loop before unlock, and restore
NVMe BAR0 if the device loses PCI config state across S3.
The SMM side continues to whitelist only the OPAL service and unlock
APMC commands and fails closed if any invariant is violated.
TEST=tested with rest of patch train
Change-Id: I86a44760a189219a95914bd3549997880fb0242b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91045
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes commit "util/amdfwtool: Move APOB_NV quirk to amdfwtool.c".
Allow the AMD_BIOS_NV_ST and AMD_BIOS_APOB_NV to end at 16MiB.
Fixes a build failure when the region is last in the FMAP.
Change-Id: Icfa5b74e98223ff5864299d4e9a2d23606935b80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91820
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Applying the attribute silences the following error and allows
compilation with GCC 15.2.
error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute
Change-Id: I33cf3219f34e297de03f67d3e73058b10930c9f8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
PSP supports A/B updates of the PSP directory structure. This
is unrelated to VBOOT's A/B update scheme. At boot the PSP
structures of partition A are verified. If A is found corrupted
partition B will used to read in the PSP files. x86 software can
then fix the A partition and switch back to the A partition.
Add functions to get, set and toggle the active boot partition used
on the next boot.
Change-Id: Ia7f2eedae5b277745cb34a0761bd1a8b61441695
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Implement the red i-dot LED in the ThinkPad logo at the display lid.
On warm reboot the LOGO LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened. (Similar to PWR LED; see change ID 88998)
Further testing on other devices running H8 EC is required!
TEST=LOGO LED is on after warm reboot on Lenovo T440p.
Reference: https://ch1p.io/t440p-leds-control-linux/#list-of-leds
Related: https://review.coreboot.org/c/coreboot/+/88998
Change-Id: I2ebba5a4c1ffc38f0c2e1b24793e4a252cc171bd
Signed-off-by: Christian Schrötter <cs@fnx.li>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91837
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Star Labs boards can continuously trigger the TCO intruder SMI.
Default the common Kconfig symbol off to avoid those spurious events.
Change-Id: I4fbdc3d0f43d814564e972afcaaac1e967fb49f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PWM_Frequency_03 changes from 200Hz to 2kHz.
The 16-inch QHD panel supports 200Hz to 2kHz, while the 16-inch 4K
panel supports 200Hz to 10kHz. Keep the shared board VBT at 2kHz for
now; the higher 10kHz value only applies to the 4K panel.
Change-Id: If5a6d1ea248132219f8c0115771fb26d9d5b228a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91870
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 2kHz.
The 14-inch 1080p panel supports 190Hz to 2kHz, so use the panel's
safe maximum instead of the old 200Hz default.
Change-Id: Ibf21bf291fecfd2b10a74bb3667549ef2f271356
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The 14-inch 4K panel supports 100Hz to 10kHz, so raise the board VBT
value to the panel's safe maximum.
Change-Id: I94694d06e09d58f92966a2c827aad52f15e1e4c6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91868
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The 12.5-inch 2K panel supports 100Hz to 10kHz, while the 12.5-inch
3K panel supports 200Hz to 25kHz. Keep the shared board VBT at 10kHz
until panel-specific selection exists.
Change-Id: Ia8bf5a324eb65698a8ba89b89cee8a9d10fba07d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91867
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The HZ panel is validated at 10kHz, so use that known-good value in
the board VBT instead of the old 200Hz default.
Change-Id: Ieaddba9a7fef42be8de2cc64f234a39dde62c25f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Restore the HZ panel VBT minimum brightness for panel entry 03 to the reference value.
Post_Min_Brightness_03 changes from 0 to 25.
Change-Id: I04ae425a1377b4a716127a0624872b74fb3eb962
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the StarBook 14-inch 1080p panel VBT timing values against the
panel datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: Ie153c6272595268565e1966b7d7773d4d068680c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91864
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the i5 panel VBT timing values against the panel datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 2000.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.
Change-Id: I717be5863d0352224eae1053db77e8d3234a396f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the StarBook 14-inch 4K panel VBT timing values against the panel
datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.
Change-Id: I941e268f6a05f74248b19eb75fc7f07f781e347c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91862
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the StarFighter panel VBT timing values against the panel datasheets for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: I382a1609aa7fee082b172ed07c761a7655a56dd3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the HZ panel VBT timing values against the panel datasheet for
panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: Icc711c3c6f105cfd6fc1dc5bbab24d9b172a924f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91860
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gnvs.c uses the global NVS definitions directly, so include
acpi/acpi_gnvs.h explicitly instead of relying on indirect headers.
Change-Id: Ifd19111a01ced3cb9bdb85ac192358e823dd3f44
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91857
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MKBP support for zork devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/morphius, verify vivaldi keyboard mapping
functional under both Linux and Win11.
Change-Id: I021454b92cdb90e2a385eee1b3d4cc0438c75132
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for reef devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/reef, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: If7a8df8469c22404e22d80fd4d116b862b6b5cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91786
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MKBP support for octopus devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/ampton, verify vivaldi keyboard mapping
functional under both Linux and Win11.
Change-Id: I31ecd87d8e9335dd4131f022370b32bf2d056b03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for hatch devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/akemi, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: I7bd222160efdd4de0d63ab9542c0d2828aac583a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for glados devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/chell, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: Ia1ea5cdece52d33f7467af0b6e1d891a04b63b94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
