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soc/qualcomm/calypso: Add initial SoC skeleton for Calypso

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This commit introduces a basic SoC framework for the Qualcomm
Calypso SoC enabling initial build integration.

Key changes:

- Add placeholder SoC callbacks to facilitate control flow from /lib
  and Qualcomm common code.
- Populate the calypso SoC directory with a copy of the X1P42100
  codebase, with SoC-specific implementations removed.

This provides a foundational structure for Calypso development
within the `soc/qualcomm/calypso` directory, ensuring the upstream
builder can successfully compile the SoC code.

This allows for incremental development and integration.

Reference Document: Calypso Hardware Register Description

BUG=b:496650089
TEST=Successfully built google/mensa with the Qualcomm Calypso SoC.

Change-Id: Iabbbf26c9e08906db2be024911061837fdf83bd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91892
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2026-03-26 20:40:08 +00:00
commit 38e8eadfa7
21 changed files with 1149 additions and 0 deletions
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67
src/soc/qualcomm/calypso/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config SOC_QUALCOMM_CALYPSO_BASE
bool
default n
select ARCH_BOOTBLOCK_ARMV8_64
select ARCH_RAMSTAGE_ARMV8_64
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
select ARM64_USE_ARCH_TIMER
select CACHE_MRC_SETTINGS
select COMMONLIB_STORAGE
select COMMONLIB_STORAGE_SD
select FIXED_UART_FOR_CONSOLE
select GENERIC_GPIO_LIB
select GENERIC_UDELAY
select HAS_RECOVERY_MRC_CACHE
select HAVE_CBFS_FILE_OPTION_BACKEND
select HAVE_LINEAR_FRAMEBUFFER
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT
select SOC_QUALCOMM_COMMON
select SOC_QUALCOMM_QCLIB_SKIP_MMU_TOGGLE
config SOC_QUALCOMM_CALYPSO
bool
select SOC_QUALCOMM_CALYPSO_BASE
default n
help
Choose this option if the mainboard is built using Calypso system-on-a-chip SoC.
if SOC_QUALCOMM_CALYPSO_BASE
config QC_BLOBS_UPSTREAM
bool "QC blobs are available in upstream repository"
select USE_QC_BLOBS
default n
help
Select based on availability of QC blobs in upstream coreboot `3rdparty/qc_blobs`.
config MEMLAYOUT_LD_FILE
string
default "src/soc/qualcomm/calypso/memlayout.ld"
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_RETURN_FROM_VERSTAGE
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_STARTS_IN_BOOTBLOCK
config BOOT_DEVICE_SPI_FLASH_BUS
int
default 0 # TODO
config UART_FOR_CONSOLE
int
default 0 # TODO
help
Select the QUP instance to be used for UART console output.
config UART_BITBANG_TX_DELAY_MS
int
default 1
endif

345
src/soc/qualcomm/calypso/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_QUALCOMM_CALYPSO_BASE),y)
decompressor-y += decompressor.c
decompressor-y += mmu.c
decompressor-y += ../common/timer.c
all-y += ../common/timer.c
all-y += ../common/gpio.c
all-y += clock.c
all-y += ../common/spi.c
all-y += ../common/qspi.c
all-y += ../common/qupv3_config.c
all-y += qcom_qup_se.c
all-y += ../common/qup_se_handler.c
all-y += ../common/qupv3_spi.c
all-y += ../common/qupv3_i2c.c
all-y += ../common/qupv3_spi.c
################################################################################
bootblock-y += bootblock.c
bootblock-y += mmu.c
bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c
################################################################################
verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
################################################################################
romstage-y += cbmem.c
romstage-y += ../common/shrm_load_reset.c
romstage-y += cpucp_load_reset.c
romstage-y += ../common/qclib.c
romstage-y += ../common/mmu.c
romstage-y += ../common/watchdog.c
romstage-y += mmu.c
romstage-y += ../common/aop_load_reset.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
################################################################################
ramstage-y += soc.c
ramstage-y += cbmem.c
ramstage-y += ../common/mmu.c
ramstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
ramstage-y += cpucp_load_reset.c
################################################################################
CPPFLAGS_common += -Isrc/soc/qualcomm/calypso/include
CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
################################################################################
# look for QC blobs if QC SoC blobs are only available in upstream else ignore
ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
ifeq ($(CONFIG_USE_QC_BLOBS),y)
CALYPSO_BLOB := $(top)/3rdparty/qc_blobs/calypso
ifeq ($(CONFIG_QC_SECURE_BOOT_BLOBS),y)
BLOB_VARIANT := secure
else
BLOB_VARIANT := non_secure
endif
DTB_DCB_BLOB_PATH := calypso
ifeq ($(CONFIG_QC_SDI_ENABLE),y)
BL31_MAKEARGS += QTI_SDI_BUILD=1
BL31_MAKEARGS += QTISECLIB_PATH=$(CALYPSO_BLOB)/qtiseclib/libqtisec_dbg.a
else
BL31_MAKEARGS += QTISECLIB_PATH=$(CALYPSO_BLOB)/qtiseclib/libqtisec.a
endif # CONFIG_QC_SDI_ENABLE
################################################################################
ifeq ($(CONFIG_QC_SDI_ENABLE),y)
QCSDI_FILE := $(CALYPSO_BLOB)/boot/QcSdi.elf
QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi
$(QCSDI_CBFS)-file := $(QCSDI_FILE)
$(QCSDI_CBFS)-type := stage
$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(QCSDI_CBFS)
endif
################################################################################
QC_SEC_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/qc_sec/qc_sec.mbn
TME_SEQ_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/tme/sequencer_ram.elf
TME_FW_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/tme/signed_firmware_soc_view.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf
@util/qualcomm/createxbl.py --mbn_version 7 -f $(objcbfs)/bootblock.raw.elf \
-o $(objcbfs)/bootblock.mbn \
-a 64 -c 64
@util/qualcomm/create_multielf.py -f $(TME_SEQ_FILE),$(TME_FW_FILE),$(QC_SEC_FILE),$(objcbfs)/bootblock.mbn \
-o $(objcbfs)/merged_bb.melf
@printf "\nqgpt.py 4K sector size\n"
@util/qualcomm/qgpt.py $(objcbfs)/merged_bb.melf \
$(objcbfs)/bootblock.bin
################################################################################
QCLIB_FILE := $(CALYPSO_BLOB)/boot/QcLib.elf
QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib
$(QCLIB_CBFS)-file := $(QCLIB_FILE)
$(QCLIB_CBFS)-type := stage
$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(QCLIB_CBFS)
################################################################################
DCB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/dcb.bin
DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb
$(DCB_CBFS)-file := $(DCB_FILE)
$(DCB_CBFS)-type := raw
$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(DCB_CBFS)
################################################################################
DTB_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/pre-ddr.dtb
DTB_CBFS := $(CONFIG_CBFS_PREFIX)/dtb
$(DTB_CBFS)-file := $(DTB_FILE)
$(DTB_CBFS)-type := raw
$(DTB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(DTB_CBFS)
################################################################################
CPR_FILE := $(CALYPSO_BLOB)/boot/$(DTB_DCB_BLOB_PATH)/cpr.bin
CPR_CBFS := $(CONFIG_CBFS_PREFIX)/cpr
$(CPR_CBFS)-file := $(CPR_FILE)
$(CPR_CBFS)-type := raw
$(CPR_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(CPR_CBFS)
################################################################################
UART_FW_FILE := $(CALYPSO_BLOB)/qup_fw/uart_fw.bin
UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
$(UART_FW_CBFS)-file := $(UART_FW_FILE)
$(UART_FW_CBFS)-type := raw
$(UART_FW_CBFS)-compression := none
cbfs-files-y += $(UART_FW_CBFS)
################################################################################
SPI_FW_FILE := $(CALYPSO_BLOB)/qup_fw/spi_fw.bin
SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw
$(SPI_FW_CBFS)-file := $(SPI_FW_FILE)
$(SPI_FW_CBFS)-type := raw
$(SPI_FW_CBFS)-compression := none
cbfs-files-y += $(SPI_FW_CBFS)
################################################################################
I2C_FW_FILE := $(CALYPSO_BLOB)/qup_fw/i2c_fw.bin
I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw
$(I2C_FW_CBFS)-file := $(I2C_FW_FILE)
$(I2C_FW_CBFS)-type := raw
$(I2C_FW_CBFS)-compression := none
cbfs-files-y += $(I2C_FW_CBFS)
################################################################################
AOP_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn
AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop
$(AOP_CBFS)-file := $(AOP_FILE)
$(AOP_CBFS)-type := payload
$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(AOP_CBFS)
################################################################################
# Rule to create aop_meta from aop.mbn
# This rule depends on aop.mbn built and the extractor script existing.
$(obj)/mainboard/$(MAINBOARDDIR)/aop_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop.mbn util/qualcomm/elf_segment_extractor.py
@echo "Extracting ELF headers and hash table segment from $< to $@"
@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
AOP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_meta
AOP_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_meta
$(AOP_META_CBFS)-file := $(AOP_META_FILE)
$(AOP_META_CBFS)-type := raw
$(AOP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(AOP_META_CBFS)
################################################################################
AOP_CFG_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn
AOP_CFG_CBFS := $(CONFIG_CBFS_PREFIX)/aop_cfg
$(AOP_CFG_CBFS)-file := $(AOP_CFG_FILE)
$(AOP_CFG_CBFS)-type := payload
$(AOP_CFG_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(AOP_CFG_CBFS)
################################################################################
# Rule to create aop_meta from aop_devcfg.mbn
# This rule depends on aop_devcfg.mbn built and the extractor script existing.
$(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/aop/aop_devcfg.mbn util/qualcomm/elf_segment_extractor.py
@echo "Extracting ELF headers and hash table segment from $< to $@"
@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
AOP_DEVCFG_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/aop_devcfg_meta
AOP_DEVCFG_META_CBFS := $(CONFIG_CBFS_PREFIX)/aop_devcfg_meta
$(AOP_DEVCFG_META_CBFS)-file := $(AOP_DEVCFG_META_FILE)
$(AOP_DEVCFG_META_CBFS)-type := raw
$(AOP_DEVCFG_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(AOP_DEVCFG_META_CBFS)
################################################################################
CPUCP_FILE := $(CALYPSO_BLOB)/cpucp/cpucp.elf
CPUCP_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp
$(CPUCP_CBFS)-file := $(CPUCP_FILE)
$(CPUCP_CBFS)-type := payload
$(CPUCP_CBFS)-compression := none
cbfs-files-y += $(CPUCP_CBFS)
################################################################################
# Rule to create cpucp_meta from cpucp.elf
# This rule depends on cpucp.elf being built and the extractor script existing.
$(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta: $(CALYPSO_BLOB)/cpucp/cpucp.elf util/qualcomm/elf_segment_extractor.py
@echo "Extracting ELF headers and hash table segment from $< to $@"
@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
CPUCP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/cpucp_meta
CPUCP_META_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_meta
$(CPUCP_META_CBFS)-file := $(CPUCP_META_FILE)
$(CPUCP_META_CBFS)-type := raw
$(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(CPUCP_META_CBFS)
################################################################################
CPUCP_DTBS_FILE := $(CALYPSO_BLOB)/cpucp/cpucp_dtbs.elf
CPUCP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_dtbs
$(CPUCP_DTBS_CBFS)-file := $(CPUCP_DTBS_FILE)
$(CPUCP_DTBS_CBFS)-type := payload
$(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(CPUCP_DTBS_CBFS)
################################################################################
SHRM_FILE := $(CALYPSO_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf
SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
$(SHRM_CBFS)-file := $(SHRM_FILE)
$(SHRM_CBFS)-type := payload
$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(SHRM_CBFS)
################################################################################
# Rule to create shrm_meta from shrm.elf
# This rule depends on shrm.elf being built and the extractor script existing.
$(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta: $(CALYPSO_BLOB)/$(BLOB_VARIANT)/shrm/shrm.elf util/qualcomm/elf_segment_extractor.py
@echo "Extracting ELF headers and hash table segment from $< to $@"
@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
SHRM_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/shrm_meta
SHRM_META_CBFS := $(CONFIG_CBFS_PREFIX)/shrm_meta
$(SHRM_META_CBFS)-file := $(SHRM_META_FILE)
$(SHRM_META_CBFS)-type := raw
$(SHRM_META_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(SHRM_META_CBFS)
################################################################################
GSI_FW_FILE := $(CALYPSO_BLOB)/qup_fw/gsi_fw.bin
GSI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/gsi_fw
$(GSI_FW_CBFS)-file := $(GSI_FW_FILE)
$(GSI_FW_CBFS)-type := raw
$(GSI_FW_CBFS)-compression := none
cbfs-files-y += $(GSI_FW_CBFS)
################################################################################
ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y)
DEVCFG_TZ_FILE := $(CALYPSO_BLOB)/qtee/tz_oem_config.mbn
DEVCFG_TZ_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzoem_cfg
$(DEVCFG_TZ_FILE_CBFS)-file := $(DEVCFG_TZ_FILE)
$(DEVCFG_TZ_FILE_CBFS)-type := payload
$(DEVCFG_TZ_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(DEVCFG_TZ_FILE_CBFS)
################################################################################
TZQTI_CFG_FILE := $(CALYPSO_BLOB)/qtee/tz_qti_config.mbn
TZQTI_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzqti_cfg
$(TZQTI_CFG_FILE_CBFS)-file := $(TZQTI_CFG_FILE)
$(TZQTI_CFG_FILE_CBFS)-type := payload
$(TZQTI_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(TZQTI_CFG_FILE_CBFS)
################################################################################
TZAC_CFG_FILE := $(CALYPSO_BLOB)/ac_policy/tz_ac_config.elf
TZAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/tzac_cfg
$(TZAC_CFG_FILE_CBFS)-file := $(TZAC_CFG_FILE)
$(TZAC_CFG_FILE_CBFS)-type := payload
$(TZAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(TZAC_CFG_FILE_CBFS)
################################################################################
HYPAC_CFG_FILE := $(CALYPSO_BLOB)/ac_policy/hyp_ac_config.elf
HYPAC_CFG_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/hypac_cfg
$(HYPAC_CFG_FILE_CBFS)-file := $(HYPAC_CFG_FILE)
$(HYPAC_CFG_FILE_CBFS)-type := payload
$(HYPAC_CFG_FILE_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(HYPAC_CFG_FILE_CBFS)
endif # ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y)
################################################################################
ifeq ($(CONFIG_QC_APDP_ENABLE),y)
APDP_FILE := $(CALYPSO_BLOB)/qtee/apdp.mbn
APDP_CBFS := $(CONFIG_CBFS_PREFIX)/apdp
$(APDP_CBFS)-file := $(APDP_FILE)
$(APDP_CBFS)-type := payload
$(APDP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(APDP_CBFS)
################################################################################
# Rule to create apdp_meta from apdp.mbn
# This rule depends on apdp.mbn being built and the extractor script existing.
$(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta: $(CALYPSO_BLOB)/qtee/apdp.mbn util/qualcomm/elf_segment_extractor.py
@echo "Extracting ELF headers and hash table segment from $< to $@"
@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
APDP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/apdp_meta
APDP_META_CBFS := $(CONFIG_CBFS_PREFIX)/apdp_meta
$(APDP_META_CBFS)-file := $(APDP_META_FILE)
$(APDP_META_CBFS)-type := raw
$(APDP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(APDP_META_CBFS)
endif # ifeq ($(CONFIG_QC_APDP_ENABLE),y)
################################################################################
ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
RAMDUMP_FILE := $(CALYPSO_BLOB)/boot/XblRamdump.elf
RAMDUMP_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump
$(RAMDUMP_CBFS)-file := $(RAMDUMP_FILE)
$(RAMDUMP_CBFS)-type := stage
$(RAMDUMP_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(RAMDUMP_CBFS)
################################################################################
# Rule to create ramdump_meta from XblRamdump.elf
# This rule depends on XblRamdump.elf being built and the extractor script existing.
$(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta: $(CALYPSO_BLOB)/boot/XblRamdump.elf util/qualcomm/elf_segment_extractor.py
@echo "Extracting ELF headers and hash table segment from $< to $@"
@util/qualcomm/elf_segment_extractor.py --eh --pht --hashtable $< $@
RAMDUMP_META_FILE := $(obj)/mainboard/$(MAINBOARDDIR)/ramdump_meta
RAMDUMP_META_CBFS := $(CONFIG_CBFS_PREFIX)/ramdump_meta
$(RAMDUMP_META_CBFS)-file := $(RAMDUMP_META_FILE)
$(RAMDUMP_META_CBFS)-type := raw
$(RAMDUMP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(RAMDUMP_META_CBFS)
endif # ifeq ($(CONFIG_QC_RAMDUMP_ENABLE),y)
endif # ifeq ($(CONFIG_USE_QC_BLOBS),y)
endif # ifeq ($(CONFIG_QC_BLOBS_UPSTREAM),y)
endif # ifeq ($(CONFIG_SOC_QUALCOMM_CALYPSO_BASE),y)

15
src/soc/qualcomm/calypso/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/mmu.h>
void bootblock_soc_early_init(void)
{
if (!CONFIG(COMPRESS_BOOTBLOCK))
soc_mmu_init();
}
void bootblock_soc_init(void)
{
/* Placeholder */
}

10
src/soc/qualcomm/calypso/cbmem.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h>
#include <console/console.h>
uintptr_t cbmem_top_chipset(void)
{
printk(BIOS_ERR, "%s: Update CBMEM TOP address.\n", __func__);
return (uintptr_t)NULL;
}

18
src/soc/qualcomm/calypso/clock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/clock.h>
void clock_configure_qspi(uint32_t hz)
{
/* placeholder */
}
void clock_enable_qup(int qup)
{
/* placeholder */
}
void clock_configure_dfsr(int qup)
{
/* placeholder */
}

8
src/soc/qualcomm/calypso/cpucp_load_reset.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/cpucp.h>
void cpucp_fw_load_reset(void)
{
/* Placeholder */
}

9
src/soc/qualcomm/calypso/decompressor.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/mmu.h>
void decompressor_soc_init(void)
{
soc_mmu_init();
}

69
src/soc/qualcomm/calypso/include/soc/addressmap.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__
#define __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__
#include <stdint.h>
#include <types.h>
/* TODO: update as per datasheet */
#define AOSS_CC_BASE 0x0C2A0000
#define QSPI_BASE 0x088DC000
#define TLMM_TILE_BASE 0x0F100000
#define GCC_BASE 0x00100000
#define NCC0_BASE 0x19A30000
#define GCC_QUPV3_WRAP0_BASE 0x142004
#define GCC_QUPV3_WRAP1_BASE 0x118004
#define GCC_QUPV3_WRAP2_BASE 0x11e004
/* CALPYSO QSPI GPIO PINS */
#define QSPI_CS GPIO(0)
#define QSPI_DATA_0 GPIO(0)
#define QSPI_DATA_1 GPIO(0)
#define QSPI_CLK GPIO(0)
#define GPIO_FUNC_QSPI_DATA_0 0
#define GPIO_FUNC_QSPI_DATA_1 0
#define GPIO_FUNC_QSPI_CLK 0
/* QUP SERIAL ENGINE BASE ADDRESSES */
/* QUPV3_0 */
#define QUP_SERIAL0_BASE 0x00B80000
#define QUP_SERIAL1_BASE 0x00B84000
#define QUP_SERIAL2_BASE 0x00B88000
#define QUP_SERIAL3_BASE 0x00B8C000
#define QUP_SERIAL4_BASE 0x00B90000
#define QUP_SERIAL5_BASE 0x00B94000
#define QUP_SERIAL6_BASE 0x00B98000
#define QUP_SERIAL7_BASE 0x00B9C000
#define QUP_WRAP0_BASE 0x00BC0000
#define QUP_0_GSI_BASE 0x00B04000
/* QUPV3_1 */
#define QUP_SERIAL8_BASE 0x00A80000
#define QUP_SERIAL9_BASE 0x00A84000
#define QUP_SERIAL10_BASE 0x00A88000
#define QUP_SERIAL11_BASE 0x00A8C000
#define QUP_SERIAL12_BASE 0x00A90000
#define QUP_SERIAL13_BASE 0x00A94000
#define QUP_SERIAL14_BASE 0x00A98000
#define QUP_SERIAL15_BASE 0x00A9C000
#define QUP_WRAP1_BASE 0x00AC0000
#define QUP_1_GSI_BASE 0x00A04000
/* QUPV3_2 */
#define QUP_SERIAL16_BASE 0x00880000
#define QUP_SERIAL17_BASE 0x00884000
#define QUP_SERIAL18_BASE 0x00888000
#define QUP_SERIAL19_BASE 0x0088C000
#define QUP_SERIAL20_BASE 0x00890000
#define QUP_SERIAL21_BASE 0x00894000
#define QUP_SERIAL22_BASE 0x00898000
#define QUP_SERIAL23_BASE 0x0089C000
#define QUP_WRAP2_BASE 0x008C0000
#define QUP_2_GSI_BASE 0x00804000
/* QUPV3_3 - Dummy Entry */
#define QUP_WRAP3_BASE 0x007C0000
#endif /* __SOC_QUALCOMM_CALYPSO_ADDRESS_MAP_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/addressmap.h>
#include <types.h>
#include <soc/clock_common.h>
#ifndef __SOC_QUALCOMM_CALYPSO_CLOCK_H__
#define __SOC_QUALCOMM_CALYPSO_CLOCK_H__
#define SRC_XO_HZ (19200 * KHz)
/* TODO: update as per datasheet */
void clock_configure_qspi(uint32_t hz);
void clock_enable_qup(int qup);
void clock_configure_dfsr(int qup);
/* Does nothing */
#define clock_reset_aop() do {} while (0)
/* Does nothing */
#define clock_reset_shrm() do {} while (0)
enum clk_qup {
QUP_WRAP0_S0,
QUP_WRAP0_S1,
QUP_WRAP0_S2,
QUP_WRAP0_S3,
QUP_WRAP0_S4,
QUP_WRAP0_S5,
QUP_WRAP0_S6,
QUP_WRAP0_S7,
QUP_WRAP1_S0,
QUP_WRAP1_S1,
QUP_WRAP1_S2,
QUP_WRAP1_S3,
QUP_WRAP1_S4,
QUP_WRAP1_S5,
QUP_WRAP1_S6,
QUP_WRAP1_S7,
QUP_WRAP2_S0,
QUP_WRAP2_S1,
QUP_WRAP2_S2,
QUP_WRAP2_S3,
QUP_WRAP2_S4,
QUP_WRAP2_S5,
QUP_WRAP2_S6,
QUP_WRAP2_S7,
};
/* Subsystem Reset */
static struct aoss *const aoss = (void *)AOSS_CC_BASE;
#endif // __SOC_QUALCOMM_CALYPSO_CLOCK_H__

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_CPUCP_H__
#define __SOC_QUALCOMM_CALYPSO_CPUCP_H__
void cpucp_fw_load_reset(void);
#endif // __SOC_QUALCOMM_CALYPSO_CPUCP_H__

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src/soc/qualcomm/calypso/include/soc/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_GPIO_H__
#define __SOC_QUALCOMM_CALYPSO_GPIO_H__
#include <types.h>
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
#define PIN(index, func1, func2, func3, func4, func5, func6) \
GPIO##index##_ADDR = (TLMM_TILE_BASE + ((index) * TLMM_GPIO_OFF_DELTA)), \
GPIO##index##_FUNC_##func1 = (1), \
GPIO##index##_FUNC_##func2 = (2), \
GPIO##index##_FUNC_##func3 = (3), \
GPIO##index##_FUNC_##func4 = (4), \
GPIO##index##_FUNC_##func5 = (5), \
GPIO##index##_FUNC_##func6 = (6)
/* TODO: update as per datasheet */
enum {
PIN(0, QUP0_SE0_L0, RES_2, RES_3, RES_4, RES_5, RES_6),
};
#endif /* __SOC_QUALCOMM_CALYPSO_GPIO_H__ */

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src/soc/qualcomm/calypso/include/soc/mmu.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_MMU_H__
#define __SOC_QUALCOMM_CALYPSO_MMU_H__
void soc_mmu_init(void);
#endif /* __SOC_QUALCOMM_CALYPSO_MMU_H__ */

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src/soc/qualcomm/calypso/include/soc/qcom_qup_se.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_QUP_SE_H__
#define __SOC_QUALCOMM_CALYPSO_QUP_SE_H__
#include <console/console.h>
#include <device/mmio.h>
#include <gpio.h>
#include <soc/addressmap.h>
#include <timer.h>
#include <types.h>
/* TODO: update as per datasheet */
enum qup_se {
QUPV3_0_SE0,
QUPV3_0_SE1,
QUPV3_0_SE2,
QUPV3_0_SE3,
QUPV3_0_SE4,
QUPV3_0_SE5,
QUPV3_0_SE6,
QUPV3_0_SE7,
QUPV3_1_SE0,
QUPV3_1_SE1,
QUPV3_1_SE2,
QUPV3_1_SE3,
QUPV3_1_SE4,
QUPV3_1_SE5,
QUPV3_1_SE6,
QUPV3_1_SE7,
QUPV3_2_SE0,
QUPV3_2_SE1,
QUPV3_2_SE2,
QUPV3_2_SE3,
QUPV3_2_SE4,
QUPV3_2_SE5,
QUPV3_2_SE6,
QUPV3_2_SE7,
QUPV3_SE_MAX,
};
struct qup {
struct qup_regs *regs;
gpio_t pin[4];
u8 func[4];
};
extern struct qup qup[QUPV3_SE_MAX];
/* TODO: update MAX_OFFSET_CFG_REG as per datasheet */
#define MAX_OFFSET_CFG_REG 0x000001c4
#endif /* __SOC_QUALCOMM_CALYPSO_QUP_SE_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_SHRM_H__
#define __SOC_QUALCOMM_CALYPSO_SHRM_H__
void shrm_fw_load_reset(void);
#endif // __SOC_QUALCOMM_CALYPSO_SHRM_H__

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_QUALCOMM_CALYPSO_UART_TX_H__
#define __SOC_QUALCOMM_CALYPSO_UART_TX_H__
/* TODO: update as per datasheet */
#define UART_TX_PIN GPIO(0)
#endif /* __SOC_QUALCOMM_CALYPSO_UART_TX_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <memlayout.h>
#include <arch/header.ld>
#include <soc/memlayout.h>
/* Copied from Qualcomm previous generation SoC X1P42100 and need cleanup */
/*
* The linker script below configures the memory layout for the Qualcomm X1P42100 SoC.
*
* The memory map and addressing scheme are implemented according to the official Qualcomm
* Hardware Reference Document (HRD) for this specific SoC.
*
* 0x10000000000 +----------------------------------------------------------+ <--------------
* | dram_space_2 | DRAM Space 2 ^
* 0x8800000000 +----------------------------------------------------------+ <--------- |
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX |
* 0x1000000000 +----------------------------------------------------------+ <--------- |
* | dram_space_1 | DRAM Space 1 |
* 0x880000000 +----------------------------------------------------------+ <--------- |
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX |
* 0x100000000 +----------------------------------------------------------+ <--------- |
* | dram_smem (Shared Memory) | ^ |
* 0xFFE00000 +----------------------------------------------------------+ | |
* | dram_llcc_lpi | | |
* 0xFF800000 +----------------------------------------------------------+ | |
* | dram_acdb | | |
* +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0xE69C0000 +----------------------------------------------------------+ | |
* | dram_display | | |
* 0xE4800000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0xD9632000 +----------------------------------------------------------+ | |
* | dram_ta | | |
* 0xD8632000 +----------------------------------------------------------+ | |
* | BL31 (ARM Trusted Firmware) | | |
* 0xD856A000 +----------------------------------------------------------+ | |
* | dram_tz (TrustZone) | | |
* 0xD8000000 +----------------------------------------------------------+ | DRAM
* | ... Usable memory ... | | |
* 0xD7800000 +----------------------------------------------------------+ | |
* | Linux Kernel Reserve | | |
* 0xC7800000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0xA1800000 +----------------------------------------------------------+ | |
* | RAMSTAGE | DRAM Space 0 |
* 0xA0800000 +----------------------------------------------------------+ | |
* | POSTRAM_CBFS_CACHE | | |
* 0x9F800000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0x91380000 +----------------------------------------------------------+ | |
* | dram_pil | | |
* 0x866C0000 +----------------------------------------------------------+ | |
* | CBMEM | | |
* +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0x85F80000 +----------------------------------------------------------+ | |
* | dram_wlan | | |
* 0x85380000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0x82800000 +----------------------------------------------------------+ | |
* | dram_adsp_rpc_heap | | |
* 0x82000000 +----------------------------------------------------------+ | |
* | dram_tz_static | | |
* 0x81F00000 +----------------------------------------------------------+ | |
* | dram_pdp | | |
* 0x81E00000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0x81CF4000 +----------------------------------------------------------+ | |
* | dram_dc_log | | |
* 0x81CE4000 +----------------------------------------------------------+ | |
* | dram_tme_log | | |
* 0x81CE0000 +----------------------------------------------------------+ | |
* | dram_tme_crashdump | | |
* 0x81CA0000 +----------------------------------------------------------+ | |
* | dram_aop_config | | |
* 0x81C80000 +----------------------------------------------------------+ | |
* | dram_aop_cmd_db | | |
* 0x81C60000 +----------------------------------------------------------+ | |
* | dram_aop | | |
* 0x81C00000 +----------------------------------------------------------+ | |
* | dram_ramdump | | |
* 0x81A40000 +----------------------------------------------------------+ | |
* | dram_xbl_log | | |
* 0x81A00000 +----------------------------------------------------------+ | |
* | ... Usable memory ... | | |
* 0x815A0000 +----------------------------------------------------------+ | |
* | dram_cpucp | | |
* 0x80E00000 +----------------------------------------------------------+ | |
* | dram_ncc | | |
* 0x80A00000 +----------------------------------------------------------+ | |
* | postram_dma_coherent_dram | | |
* 0x80004000 +----------------------------------------------------------+ | |
* | POSTRAM STACK | v v
* 0x80000000 +----------------------------------------------------------+ <--------------
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX
* 0x24060000 +----------------------------------------------------------+ <---------
* | shrm | SHRM
* 0x24040000 +----------------------------------------------------------+ <---------
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX
* 0x1CB40000 +----------------------------------------------------------+ <---------
* | CPUCP |
* 0x1CB00000 +----------------------------------------------------------+ <---------
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX
* 0x14A80000 +----------------------------------------------------------+ <---------
* | auth_metadata | ^
* 0x14A7E000 +----------------------------------------------------------+ |
* | debug_policy | |
* 0x14A7D000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x14A59000 +----------------------------------------------------------+ |
* | OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE | |
* 0x14A38000 +----------------------------------------------------------+ |
* | PRERAM_CBMEM_CONSOLE | |
* 0x14A30000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x14A1A000 +----------------------------------------------------------+ |
* | CPR | |
* 0x14A17000 +----------------------------------------------------------+ |
* | qclib | |
* 0x14897000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x14891000 +----------------------------------------------------------+ |
* | apdp_ramdump_meta | |
* 0x14890000 +----------------------------------------------------------+ |
* | aop_blob_meta | |
* 0x1488C000 +----------------------------------------------------------+ |
* | qc_blob_meta | |
* 0x14888000 +----------------------------------------------------------+ |
* | ddr_training | |
* 0x14878000 +----------------------------------------------------------+ |
* | dtb (Device Tree Blob) | |
* 0x14870000 +----------------------------------------------------------+ |
* | dcb (DDR Config Block) | |
* 0x14862000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x14860C00 +----------------------------------------------------------+ |
* | FMAP_CACHE | |
* 0x14861800 +----------------------------------------------------------+ BSRAM
* | CBFS_MCACHE | |
* 0x1485C000 +----------------------------------------------------------+ |
* | qclib_serial_log | |
* 0x1485B000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x14859000 +----------------------------------------------------------+ |
* | preram_dma_coherent_dram | |
* 0x14857000 +----------------------------------------------------------+ |
* | VBOOT2_WORK | |
* 0x14854000 +----------------------------------------------------------+ |
* | PRERAM STACK | |
* 0x14850000 +----------------------------------------------------------+ |
* | TTB (Translation Table Base) | |
* 0x14842000 +----------------------------------------------------------+ |
* | TIMESTAMP | |
* 0x14841C00 +----------------------------------------------------------+ |
* | PRERAM_CBFS_CACHE | |
* 0x14828000 +----------------------------------------------------------+ |
* | BOOTBLOCK | |
* 0x14819000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x14815000 +----------------------------------------------------------+ |
* | pbl_timestamps | v
* 0x14800000 +----------------------------------------------------------+ <---------
* | ... (Large Address Gap) ... |
* +----------------------------------------------------------+
* | ... Usable memory ... |
* 0x146AC000 +----------------------------------------------------------+ <---------
* | WATCHDOG_TOMBSTONE | ^
* 0x146ABFFC +----------------------------------------------------------+ |
* | ddr_information | |
* 0x146ABFE8 +----------------------------------------------------------+ |
* | shared_imem | |
* 0x146AA000 +----------------------------------------------------------+ |
* | aop_imem | |
* 0x146A8000 +----------------------------------------------------------+ SSRAM
* | qdss_usb_trace | |
* 0x146A6000 +----------------------------------------------------------+ |
* | ... Usable memory ... | |
* 0x146A5000 +----------------------------------------------------------+ |
* | AOP SDI | |
* 0x14699000 +----------------------------------------------------------+ |
* | Reserved for QSEE | v
* 0x14680000 +----------------------------------------------------------+ <---------
* | ... (Memory not mapped: Unavailable) ... | XXXXXXXXX
* 0x0B100000 +----------------------------------------------------------+ <---------
* | ... Usable memory ... | ^
* 0x0B0E8000 +----------------------------------------------------------+ |
* | aop_data_ram | |
* 0x0B0E0000 +----------------------------------------------------------+ AOP SRAM
* | ... Usable memory ... | |
* 0x0B018000 +----------------------------------------------------------+ |
* | aop_code_ram | v
* 0x0B000000 +----------------------------------------------------------+ <---------
*
*/
SECTIONS
{
AOPSRAM_START(0x0B000000)
REGION(aop_code_ram, 0x0B000000, 0x18000, 4K)
REGION(aop_data_ram, 0x0B0E0000, 0x8000, 4K)
AOPSRAM_END(0x0B100000)
SSRAM_START(0x14680000)
REGION(qsee, 0x14680000, 100K, 4K)
REGION(aop_sdi, 0x14699000, 48K, 4K)
REGION(qdss_usb_trace, 0x146A6000, 8K, 4K)
REGION(aop_imem, 0x146A8000, 8K, 4K)
REGION(shared_imem, 0x146AA000, 0x1000, 4K)
REGION(ddr_information, 0x146ABFE8, 16, 8)
WATCHDOG_TOMBSTONE(0x146ABFFC, 4)
SSRAM_END(0x146AC000)
BSRAM_START(0x14800000)
REGION(pbl_timestamps, 0x14800000, 84K, 4K)
BOOTBLOCK(0x14819000, 60K)
PRERAM_CBFS_CACHE(0x14828000, 103K)
TIMESTAMP(0x14841C00, 1K)
TTB(0x14842000, 56K)
PRERAM_STACK(0x14850000, 16K)
VBOOT2_WORK(0x14854000, 12K)
PRERAM_DMA_COHERENT(0x14858000, 8K)
REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
CBFS_MCACHE(0x1485C000,22K)
FMAP_CACHE(0x14861800, 2K)
REGION(dcb, 0x14862000, 56K, 4K)
REGION(dtb, 0x14870000, 32K, 4K)
REGION(ddr_training, 0x14878000, 64K, 4K)
REGION(qc_blob_meta, 0x14888000, 16K, 4K)
REGION(aop_blob_meta, 0x1488c000, 16K, 4K)
REGION(apdp_ramdump_meta, 0x14890000, 4K, 4K)
REGION(qclib, 0x14897000, 1536K, 4K)
REGION(cpr_settings, 0x14A17000, 12K, 4K)
PRERAM_CBMEM_CONSOLE(0x14A30000, 32K)
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14A38000, 132K)
REGION(debug_policy, 0x14A7D000 , 4K, 4K)
REGION(auth_metadata, 0x14A7E000, 8K, 4K)
BSRAM_END(0x14A80000)
REGION(cpucp, 0x1CB00000, 256K , 4K)
REGION(shrm, 0x24040000, 128K , 4K)
DRAM_START(0x80000000)
POSTRAM_STACK(0x80000000, 32K)
POSTRAM_DMA_COHERENT(0x8000C000, 16K)
REGION(dram_ncc, 0x80A00000, 0x400000, 4K)
REGION(dram_cpucp, 0x80E00000, 0x7A0000, 4K)
REGION(dram_xbl_log, 0x81A00000, 0x40000, 4K)
REGION(dram_ramdump, 0x81A40000, 0x1C0000, 4K)
REGION(dram_aop, 0x81C00000, 0x60000, 4K)
REGION(dram_aop_cmd_db, 0x81C60000, 0x20000, 4K)
REGION(dram_aop_config, 0x81C80000, 0x20000, 4K)
REGION(dram_tme_crashdump, 0x81CA0000, 0x40000, 4K)
REGION(dram_tme_log, 0x81CE0000, 0x4000, 4K)
REGION(dram_dc_log, 0x81CE4000, 0x10000, 4K)
REGION(dram_pdp, 0x81E00000, 0x100000, 4K)
REGION(dram_tz_static, 0x81F00000, 0x100000, 4K)
REGION(dram_adsp_rpc_heap, 0x82000000, 0x800000, 4K)
REGION(dram_wlan, 0x85380000, 0xC00000, 4K)
REGION(dram_pil, 0x866C0000, 0xACC0000, 4K)
POSTRAM_CBFS_CACHE(0x9F800000, 16M)
RAMSTAGE(0xA0800000, 16M)
REGION(dram_tz, 0xD8000000, 0x56A000, 4K)
BL31(0xD856A000, 800K)
REGION(dram_ta, 0xD8632000, 0x1000000, 4K)
REGION(dram_display, 0xE4800000, 0x21C0000, 4K)
REGION(dram_llcc_lpi, 0xFF800000, 0x600000, 4K)
REGION(dram_smem, 0xFFE00000, 0x200000, 4K)
DRAM_END(0x100000000)
/*
* Define the address range limits for fragmented DRAM regions.
*
* These regions, `dram_space_1` and `dram_space_2`, are used to map physical
* memory beyond the initial `_dram` region. The MMU configuration logic in
* `mmu.c` uses `REGION_SIZE()` to dynamically size these ranges based on the
* total system DRAM capacity, which is determined by the QCLib.
*
* Example for a 16GB DRAM system:
* - `_dram` (2GB): 0x80000000 - 0x100000000
* - `_dram_space_1` (14GB): 0x880000000 - 0x440000000 (0x880000000 + 14GB)
*
* Note: The example memory addresses are for illustration and depend on the
* platform's specific memory map.
*/
REGION(dram_space_1, 0x880000000, 0x780000000, 4K)
REGION(dram_space_2, 0x8800000000, 0x7800000000, 4K)
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <symbols.h>
#include <arch/mmu.h>
#include <arch/cache.h>
#include <soc/mmu.h>
#include <soc/mmu_common.h>
#include <soc/symbols_common.h>
void soc_mmu_init(void)
{
mmu_init();
mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM);
mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
UNCACHED_RAM);
mmu_enable();
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/pcie.h>
/* Enable PIPE clock */
int qcom_dw_pcie_enable_pipe_clock(void)
{
/* placeholder */
return 0;
}
/* Enable controller specific clocks */
int32_t qcom_dw_pcie_enable_clock(void)
{
/* placeholder */
return 0;
}
/* Turn on NVMe */
void gcom_pcie_power_on_ep(void)
{
/* placeholder */
}
void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg)
{
/* placeholder */
}

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src/soc/qualcomm/calypso/qclib.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <soc/qclib_common.h>
__weak int qclib_mainboard_override(struct qclib_cb_if_table *table) { return 0; }
int qclib_soc_override(struct qclib_cb_if_table *table)
{
/* hook for platform specific policy configuration */
if (qclib_mainboard_override(table)) {
printk(BIOS_ERR, "qclib_mainboard_override failed\n");
return -1;
}
return 0;
}

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src/soc/qualcomm/calypso/qcom_qup_se.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/qcom_qup_se.h>
/* TODO: update QUP entries as per datasheet */
struct qup qup[QUPV3_SE_MAX] = {
};

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <soc/mmu.h>
#include <soc/mmu_common.h>
#include <soc/symbols_common.h>
#include <soc/pcie.h>
#include <soc/clock.h>
#include <soc/cpucp.h>
#include <program_loading.h>
static struct device_operations pci_domain_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources
};
static void soc_read_resources(struct device *dev)
{
/* placeholder */
}
static void qtee_fw_config_load(void)
{
if (!CONFIG(ARM64_USE_SECURE_OS))
return;
struct prog devcfg_tz = PROG_INIT(PROG_PAYLOAD,
CONFIG_CBFS_PREFIX"/tzoem_cfg");
if (!selfload(&devcfg_tz))
die("devcfg_tz load failed");
struct prog tzqti_cfg = PROG_INIT(PROG_PAYLOAD,
CONFIG_CBFS_PREFIX"/tzqti_cfg");
if (!selfload(&tzqti_cfg))
die("tzqti_cfg load failed");
struct prog tzac_cfg = PROG_INIT(PROG_PAYLOAD,
CONFIG_CBFS_PREFIX"/tzac_cfg");
if (!selfload(&tzac_cfg))
die("tzac_cfg load failed");
struct prog hypac_cfg = PROG_INIT(PROG_PAYLOAD,
CONFIG_CBFS_PREFIX"/hypac_cfg");
if (!selfload(&hypac_cfg))
die("hypac_cfg load failed");
}
static void soc_init(struct device *dev)
{
cpucp_fw_load_reset();
qtee_fw_config_load();
}
static struct device_operations soc_ops = {
.read_resources = soc_read_resources,
.set_resources = noop_set_resources,
.init = soc_init,
};
static void enable_soc_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
if (mainboard_needs_pcie_init())
dev->ops = &pci_domain_ops;
else
printk(BIOS_DEBUG, "Skip setting PCIe ops\n");
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &soc_ops;
}
struct chip_operations soc_qualcomm_calypso_ops = {
.name = "Calypso",
.enable_dev = enable_soc_dev,
};