mb/google/mensa: Add initial support for Mensa

This commit introduces basic support for the google/mensa mainboard,
based on the Qualcomm Calypso SoC.

Changes:

- Add placeholder mainboard callbacks to enable control flow from /lib
  and Qualcomm SoC code.
- Populate the bluey mainboard directory with a copy of the bluey
  codebase, removing SoC/mainboard-specific implementations.

This provides a minimal working build for google/mensa, allowing
upstream builders to compile the mainboard. This facilitates easier
verification of subsequent changes.

BUG=b:4966500890
TEST=Successfully built google/mensa with Qualcomm Calypso SoC.

Change-Id: Id30a766c1bc6b37a6d35ba933c207951ab83f4d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/mainboard/google/mensa/Kconfig

@@ -0,0 +1,97 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_GOOGLE_MENSA_COMMON
+	def_bool n
+	select COMMON_CBFS_SPI_WRAPPER
+	# FIXME: keep ADB for development phase
+	select GBB_FLAG_ENABLE_ADB if VBOOT
+	select MAINBOARD_HAS_CHROMEOS
+	select SPI_FLASH
+	select SPI_FLASH_FORCE_4_BYTE_ADDR_MODE
+	select SPI_FLASH_INCLUDE_ALL_DRIVERS
+
+config BOARD_GOOGLE_BASEBOARD_MENSA
+	def_bool n
+	select BOARD_GOOGLE_MENSA_COMMON
+
+config BOARD_GOOGLE_MODEL_MENSA
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_MENSA
+	select BOARD_ROMSIZE_KB_32768
+	select EC_GOOGLE_CHROMEEC_BATTERY_SOC_DYNAMIC
+	select MAINBOARD_HAS_CHROME_EC
+	select MAINBOARD_HAS_GOOGLE_TPM
+
+config BOARD_GOOGLE_MENSA
+	select BOARD_GOOGLE_MODEL_MENSA
+	select SOC_QUALCOMM_CALYPSO
+
+if BOARD_GOOGLE_MENSA_COMMON
+
+config MAINBOARD_DIR
+	default "google/mensa"
+
+config MAINBOARD_HAS_GOOGLE_TPM
+	bool
+	default n
+	select I2C_TPM
+	select MAINBOARD_HAS_TPM2
+	select TPM_GOOGLE_TI50
+	help
+	  Enable this option if your mainboard is equipped with Google TPM aka GSC.
+
+config MAINBOARD_HAS_CHROME_EC
+	bool
+	default n
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_RTC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_GOOGLE_CHROMEEC_SWITCHES if VBOOT
+	select RTC
+	help
+	  Enable this option if your mainboard is equipped with Chrome EC.
+
+config MAINBOARD_VENDOR
+	string
+	default "Google"
+
+config VBOOT
+	select VBOOT_ALWAYS_ENABLE_DISPLAY
+	select VBOOT_LID_SWITCH if MAINBOARD_HAS_CHROME_EC
+	select VBOOT_NO_BOARD_SUPPORT if !MAINBOARD_HAS_CHROME_EC
+	select VBOOT_VBNV_FLASH
+
+##########################################################
+#### Update below when adding a new derivative board. ####
+##########################################################
+
+config MAINBOARD_PART_NUMBER
+	default "Mensa" if BOARD_GOOGLE_MENSA
+
+config DRIVER_TPM_I2C_BUS
+	depends on I2C_TPM
+	hex
+	default 0x0 # TODO
+
+config DRIVER_TPM_I2C_ADDR
+	default 0x50
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	depends on EC_GOOGLE_CHROMEEC
+	hex
+	default 0x0 # TODO
+
+config MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT
+	depends on TPM_GOOGLE_TI50
+	int
+	default 0 # TODO
+	help
+	  This option specifies the GPIO pin number on the mainboard that is
+	  used for the interrupt line from the Google Security Chip (GSC) to the
+	  Application Processor (AP).
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if MAINBOARD_HAS_GOOGLE_TPM
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nogsc.fmd"
+
+endif # BOARD_GOOGLE_MENSA_COMMON

src/mainboard/google/mensa/Kconfig.name

@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+comment "Mensa (Qualcomm Calypso)"
+
+config BOARD_GOOGLE_MENSA
+	bool "->  Mensa"

src/mainboard/google/mensa/Makefile.mk

@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+all-y += boardid.c
+all-y += chromeos.c
+ifneq ($(CONFIG_MISSING_BOARD_RESET),y)
+all-y += reset.c
+endif
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c

src/mainboard/google/mensa/board.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GOOGLE_MENSA_BOARD_H
+#define MAINBOARD_GOOGLE_MENSA_BOARD_H
+
+#include <assert.h>
+#include <gpio.h>
+
+/* TODO: update as per datasheet */
+#define GPIO_AP_EC_INT		GPIO(0)
+#define GPIO_GSC_AP_INT		GPIO(0)
+
+void setup_chromeos_gpios(void);
+
+#endif /* MAINBOARD_GOOGLE_MENSA_BOARD_H */

src/mainboard/google/mensa/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Mensa reference board with Calypso SoC
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/mensa/boardid.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+
+uint32_t board_id(void)
+{
+	static uint32_t id = UNDEFINED_STRAPPING_ID;
+	/* Placeholder */
+	return id;
+}
+
+uint32_t sku_id(void)
+{
+	static uint32_t id = UNDEFINED_STRAPPING_ID;
+	/* Placeholder */
+	return id;
+}

src/mainboard/google/mensa/bootblock.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/qupv3_i2c_common.h>
+#include <soc/qcom_qup_se.h>
+#include <soc/qupv3_spi_common.h>
+#include "board.h"
+
+void bootblock_mainboard_init(void)
+{
+	setup_chromeos_gpios();
+
+	if (CONFIG(I2C_TPM))
+		i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */
+
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */
+}

src/mainboard/google/mensa/chromeos-nogsc.fmd

@@ -0,0 +1,45 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+FLASH@0x0 CONFIG_ROM_SIZE {
+	WP_RO 8M {
+		RO_SECTION {
+			BOOTBLOCK 512K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_VPD(PRESERVE) 16K
+	}
+
+	RW_MISC 184K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 4K {
+			SHARED_DATA
+		}
+		RW_VPD(PRESERVE) 32K
+		RW_NVRAM(PRESERVE) 16K
+	}
+
+	RW_SECTION_A 8704K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+	RW_SECTION_B 8704K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_LEGACY(CBFS)
+
+	RW_UNUSED 3840K
+
+	RW_CDT 256K
+}

src/mainboard/google/mensa/chromeos.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot/coreboot_tables.h>
+#include <bootmode.h>
+#include <drivers/tpm/cr50.h>
+#include "board.h"
+
+void setup_chromeos_gpios(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		gpio_input_pullup(GPIO_AP_EC_INT);
+
+	if (CONFIG(TPM_GOOGLE_TI50))
+		gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	/* TODO: Add required GPIO after referring to the schematics */
+	const struct lb_gpio chromeos_gpios[] = {
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+		{GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
+			"EC interrupt"},
+#endif
+#if CONFIG(TPM_GOOGLE_TI50)
+		{GPIO_GSC_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_GSC_AP_INT),
+			"TPM interrupt"},
+#endif
+	};
+
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int cr50_plat_irq_status(void)
+{
+	return gpio_irq_status(GPIO_GSC_AP_INT);
+}

src/mainboard/google/mensa/chromeos.fmd

@@ -0,0 +1,44 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+FLASH@0x0 CONFIG_ROM_SIZE {
+	WP_RO 8M {
+		RO_SECTION {
+			BOOTBLOCK 512K
+			FMAP 4K
+			COREBOOT(CBFS)
+			GBB 0x2f00
+			RO_FRID 0x100
+		}
+		RO_GSCVD 8K
+		RO_VPD(PRESERVE) 16K
+	}
+
+	RW_MISC 184K {
+		UNIFIED_MRC_CACHE(PRESERVE) 128K {
+			RECOVERY_MRC_CACHE 64K
+			RW_MRC_CACHE 64K
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 4K {
+			SHARED_DATA
+		}
+		RW_VPD(PRESERVE) 32K
+		RW_NVRAM(PRESERVE) 16K
+	}
+
+	RW_SECTION_A 8704K {
+		VBLOCK_A 8K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 256
+	}
+
+	RW_SECTION_B 8704K {
+		VBLOCK_B 8K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 256
+	}
+
+	RW_UNUSED 4M
+
+	RW_LEGACY(CBFS)
+}

src/mainboard/google/mensa/devicetree.cb

@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/qualcomm/calypso
+	device cpu_cluster 0 on end
+	device domain 0 on end
+end

src/mainboard/google/mensa/mainboard.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/pcie.h>
+
+bool mainboard_needs_pcie_init(void)
+{
+	/* Placeholder */
+	return false;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	/* Placeholder */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* Placeholder */
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+	.init = mainboard_init,
+};

src/mainboard/google/mensa/reset.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <ec/google/chromeec/ec.h>
+#include <reset.h>
+
+/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
+   but this works well enough for our purposes. */
+void do_board_reset(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		google_chromeec_reboot(EC_REBOOT_COLD, EC_REBOOT_FLAG_IMMEDIATE);
+}

src/mainboard/google/mensa/romstage.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/stages.h>
+
+void platform_romstage_main(void)
+{
+	/* Placeholder */
+}
+
+void platform_romstage_postram(void)
+{
+	/* Placeholder */
+}