In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.
The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
and toggling PCH_WAKE_L on the EC console.
Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The clock output and I2S1 GPIO pins must be correctly configured so we can
initialize the audio system.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: Ie0f283ab8948b0d9ac713eec3bc7c8ae72949330
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176212
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The "external peripheral 1" pinmux name should be changed as EXTPERIPH1.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: I9d78e9dbdf9a94baf2a634c4dcf5c7cc6eca69ba
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176215
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
To enable audio playback, the I2S (currently only I2S1 is configured) and audio
codec (external peripheral 1) must be first configured.
Note due to Tegra1x4 audio hardware design, we need to enable all audio
peripherals on AHUB.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan; Able to readl(I2Sreg).
BRANCH=none
Change-Id: Ie5c8a95f385305870745af7aeb40d7f7da8bbc0b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176104
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Some peripherals, like audio codecs, need clock outputs from Tegra chip.
The new clock_external_output(clk_id) allows enabling any of the three clock
outputs.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: I05a1ffb80077d3b14751bfa0e7c47d541a103a08
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176108
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Drop a lot of u-boot-isms and share common TIS API
between I2C driver and LPC driver.
BUG=none
TEST=Boot tested on pit
BRANCH=none
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e
Reviewed-on: https://chromium-review.googlesource.com/175670
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=ran "cbmem" on nyan and saw timestamps.
Change-Id: Id1a0f32c4278e47b2f8c31492e87c0bc899adb50
Reviewed-on: https://chromium-review.googlesource.com/176172
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For most Tegra peripherals the source clock mapping is the same. However for
some peripherals like HOST1X or AUDIO parts, the source ID has totally different
meanings. U-Boot solved this by creating a huge peripheral source clock table.
For Coreboot, since there are fewer peripherals to setup, we want to do this by
two APIs: clock_configure_source() for regular peripherals, and
clock_configure_irregular_source() for components with different clock source
mappings (you must find the real meanings in TRM).
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
BRANCH=none
Change-Id: I7820768c577c8cfcccb6cbb14a5e0b1fe0fdc50f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176109
The gpe0 block's size was being misreported. Correct
the gpe0 size and use make the FADT fields be more
robust instead instead of hand calculating fields that
are the based on the same size.
This change correctly enables GPE events in the kernel.
Confirmed this by using iotools read the gpe_cnt register.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Confirmed EC's GPE event is enabled (but
still not working).
Change-Id: I415710f7fec2e95cecee3bf679ee673dacc27480
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176271
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
- C-state table based on static config
MWAIT values are from ref code for non-S0ix config
C6 substate 8 is ignored by the kernel as it violates the CPUID
but it is left in as the other substate may not work.
- P-state table generated with proper ratio and VID values
relies on having the package power msr set to magic value
as the power-on default is wrong
- T-state table uses static table
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175742
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
The bus clock speed is needed when building ACPI P-state tables
so extract that function and have the value be saved in pattrs.
The various IACORE values are also needed, but rather than have
the ACPI code to the bit manipulation have the pattrs store an
array of the possible values for it to use directly.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi
Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
As far as I can tell turbo enabling behaves like
it did on haswell so use the standard code.
There are also some magic values to set in some magic
MSRs related to turbo and package power so they report
correctly.
The L2 cache shrink is enabled and a threshold is set
that makes both dual and quad core happy.
C1E is disabled to match the reference code.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This required changing value/mask types to uint64_t.
Another option would be to use id field to select low or high
32 bits of the MSR and set them independently.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi
Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176304
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Back when the code which got very basic things set up on the main CPUs was
committed, there was some late arriving review feedback that wasn't addressed.
This change goes back and addresses some of that feedback by renaming things
to maincpu instead of cpug, and reducing the alignment of the assembly.
The stack is still passed in from the C code because even though we always use
the same stack now, in the future we may want to start additional CPUs with
different stacks. I also kept the name maincpu_setup (originally cpug_setup)
instead of renaming it maincpu_enter because it should never be called
directly and doesn't "enter" the new CPU, it's run when the CPU comes out of
reset and gets some basic things setup for the main code written in C.
BUG=None
TEST=Booted on nyan.
BRANCH=None
Change-Id: Ia8e9fd07f9753f9ebcd51f29ca6876850f5380b7
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175933
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The superio.asl file allows for the mainboard to hang
devices off of the LPC bus in ACPI. Include the keyboard
controller, EC memory map, and host interface's resources.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted resource reservations in dmesg.
Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176134
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The mainboard needs an opportunity to hang devices off of
the LPC device. Therefore, provide this opportunity for the
mainboard.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Buit and booted with keyboard. Keys work.
Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176133
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix the SMI and SCI gpios for Rambi. Also, add in the
EC callbacks for the SMI handler. Note that the handler
for GPI SMIs has not been tested yet as baytrail chipset
code doesn't yet support setting up those configurations
yet.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts
for the EC's SCI GPI. Also was able to see Chrome EC messages
with CONFIG_DEBUG_SMI and powering down at the dev screen.
Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The IRQs used for devices that are in acpi mode are added as well
as the IRQ defitions for the dedicated GPIO IRQ routing.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built.
Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176120
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch changes some of the early clock initialization code to max
out the AVP clock rate at 300MHz as soon as possible (which will
hopefully speed up boot time). Instead of temporarily switching it to
CLK_M (from PLLP at 1MHz), we just set up PLLC (600MHz) extra early and
move it straight to there with a divisor of 2. This also inadvertently
affects the AHB and APB bus clocks (HCLK and PCLK), so we do what we can
with the tiny 2-bit divisors we have to turn that down a little (leading
to HCLK = 75MHz and PCLK = 18.75MHz). This is still way higher than the
6MHz our former code would put them to, and thus conveniently solves our
USB FIFO underrun problems.
BUG=None
TEST=None
Change-Id: I1e68359a6f69370ddfcf1a634da043d6676b9d7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175489
Baytrail has a configurable SCI irq. Add support for
properly configuring SCI irq. Note that it is currently
fixed to IRQ9, but the code supports setting it to the
other supported values. The current mainboards using
baytrail defer the madt IRQ override information to the
chipset.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted 'SCI is IRQ9' message.
Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176075
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
These changes to the eMMC pads allows the kernel to see the
eMMC device. One is able to install onto the eMMC device, and
the kernel is loaded and booted from eMMC device. Note, that
it may not fully boot because of other issues such as
not-completely working ACPI support.
BUG=chrome-os-partner:22580
BRANCH=None
TEST=booted off of usb drive. can see eMMC device.
Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
First step in cleanup is to at least get rid of junk
we don't need.
BUG=None
TEST=Builds and boots to dev screen
BRANCH=None
Change-Id: I0a31995f0de481e27805cbcec4cdbc905ee00d9e
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176023
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
For some mysterious reason GPIO_S0_NC22 is making the eDP panel
go entirely white when it is configured with internal pullup.
Since these (supposedly XDP related) pins are unknown functionality
lets set them to GPIO_DEFAULT instead of GPIO_NC.
Additionally the VBIOS is being changed to issue int15 callback
to determine the boot graphics device. If we list both LFP and EFP
then the dev/rec screens will show on the panel when HDMI is not
attached and otherwise will display on HDMI.
BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi, see firmware/kernel screens on the panel
when HDMI is not attached, and firmware screens on the panel and
kernel screens on both when HDMI is attached.
Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175952
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The TPM driver expects to call i2c_read with zero address length. The i2c
driver wasn't prepared to handle that particularly in the case of reads
because it expected to send an address before switching over to read mode for
the data. This change also fixes up the read and write calls to consistently
be read32 and write32 instead of readl and writel.
BUG=None
TEST=Saw the TPM initialized successfully in coreboot.
BRANCH=None
Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175966
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Previously the only path through memory init and coreboot was
hardcoding S5. Therefore all S3 paths would not be taken. Allow
for S3 resume to work by enabling the proper control paths in
romstage.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=While in kernel 'echo mem > /sys/power/state'. Board went
into S3. Power button press resumed back into kernel.
Change-Id: I3cbae73223f0d71c74eb3d6b7c25d1b32318ab3e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175940
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
These are almost not worth their own CL but I did not want to clutter
up a later CL with them.
BUG=None
TEST=Build, boots, get graphics
BRANCH=None
Change-Id: I16489b767ce01addd522528889878bf5875d197e
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175889
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This code has got just enough SOC special-cases in it that
it should be in tegra124. Also, long term, we hope to blow
the file into bits and disperse its functions into
display.c
BUG=None
TEST=Build, boot, see graphics
BRANCH=None
Change-Id: Ifda97b24eb678f9c4ff5a967e2a92ee2512c5081
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175830
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Rambi currently has more than 16 memory ranges. Because of
this libpayload is silently dropping them and the full amount
of memory is not being properly wiped. Correct this by bumping
the number of ranges to 32.
BUG=None
BRANCH=None
TEST=Built and booted rambi. Noted that the full amount of memory
was being properly wiped.
Change-Id: Ida456decf2498cb1547c0ceef23df446a975606b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175792
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Set up two new PLLs in the early clock code. Clear reset and enable
clocks using the standrd function called from mainboard_init. Remove
more hardcodes from display startup.
This should be the end of moving clock code around. Next step is to
remove all the display programming hardcodes for front porch, back porch,
etc. and use the settings from the coreboot device tree.
BUG=None
TEST=Build, boot, see graphics
BRANCH=None
Change-Id: I324e57f665bbd11c1d09fb4b9ec14646d0785e5f
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175732
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
We can use the mainboard clock startup for this.
This is Step 1. I'm doing this in pieces so bisect is
easy if needed.
BUG=None
TEST=build and boot and see dev mode graphics
BRANCH=None
Change-Id: Id6d5a06b550c44c983aed42c639145cf46e301ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175656
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The FADT for baytrail had incorrect offsets leading to
the kernel spewing a huge mess of ACPI errors. Fix these offsets
to be initialized in the chipset code.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted into kernel on rambi. Login screen comes up.
Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175663
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.
There are still a lot of ACPI errors in the kernel with this
change, though.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This enables flow control and sets the REQ_SEL field according
to the SPI bus.
Since REQ_SEL is just a constant that is associated with each
channel, a member is added to the tegra_spi_regs struct to hold
the appropriate value.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I037aee7e2d422e24a4cbcbc75280ec3c93d3e7bd
Reviewed-on: https://chromium-review.googlesource.com/175630
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This is needed to let the kernel know it can control everything
and not to disable features.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175629
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Populate the PCI mmio region from NVS TOLM variable.
Other regions are fixed.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175628
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds the PCI configuration region table to baytrail.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is a lot of NVS allocated to things that are not really
used. Most of these are removed and some are moved around.
Thermals are expected to be handled with DPTF so I've removed
that bit of code but have not yet cleaned up the thermal zone.
I left in the SIO BARs since I think we will need those still
even though they may need work still.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The top of low memory is also the start of the region where
PCIe resources are allocated. This needs to be passed in
ACPI but is only readable from IOSF.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.
Add a region for the "abort page" documented in the EDS.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This shortens the grostesquely huge APBDMACHAN_* defines by
removing unecessary prefixes. Names of fields which appeared at
the end of these huge #defines are preserved as they are
presented in the manual, so searching for them is still easy.
The goal is to make it so that we can actually use the #defines
without the code becoming a hideous, line-broken mess. As they were,
the #defines made code so ugly that it actually became less readable.
Additionally, a couple trivial issues were found and fixed:
- Removes duplicate AHB bus width #defines
- Removes a non-sensical #define that seems to be a result of an
incompleted copy+paste job.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I72195ff08ef51bb645a1e1ae5a11346998a12635
Reviewed-on: https://chromium-review.googlesource.com/175631
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Add a graphics_clock function which is where we intend to do all clock
graphics init. This is modeled on how we are doing the UART clock; keep
it all in one place, not spread everywhere. Add sor_clock_{start,stop}
functions. We must start and stop the SOR clocks beore we mess with the
plldp.
BUG=None
TEST=This code builds and boots and shows graphics and depth charge screen.
BRANCH=None
Change-Id: Ida4a73f9020e5542f16d2ab0793fb2116156d562
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175162
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
These need to be supported for graphics.
BUG=None
TEST=Build and boot and it all still works
BRANCH=None
Change-Id: Ie02cbd3012b320bb59be9e0fb899c09000f29a1b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175539
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
- a few clock gating bits were set improperly and was preventing
the system from transitioning out of S0 state.
- the XHCCI registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control. This was causing memory corruption.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver
Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Low system tables are in this region, and it is probably safer
to keep ASEG reserved.
Also keep the region used by ramoops from being used by the OS
and from being cleared by developer mode boots.
Lots more work needed to make the ACPI tables fully functional.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI
Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.
This is hopefully just temporary until the issues with XHCI
can be worked out.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi
Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
