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rambi: Enable USB boot with EHCI controller

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This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.

This is hopefully just temporary until the issues with XHCI
can be worked out.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
This commit is contained in:
Duncan Laurie 2013-11-01 13:35:32 -07:00 • committed by chrome-internal-fetch
commit fcf3950c0a
2 changed files with 19 additions and 1 deletions
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2
payloads/libpayload/configs/config.rambi
View file

@ -57,7 +57,7 @@ CONFIG_LP_NVRAM=y
CONFIG_LP_USB=y
# CONFIG_LP_USB_UHCI is not set
# CONFIG_LP_USB_OHCI is not set
# CONFIG_LP_USB_EHCI is not set
CONFIG_LP_USB_EHCI=y
CONFIG_LP_USB_XHCI=y
CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y

18
src/mainboard/google/rambi/devicetree.cb
View file

@ -5,6 +5,24 @@ chip soc/intel/baytrail
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
register "usb_route_to_xhci" = "0"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"
register "usb3_port_disable_mask" = "0x0"
# USB PHY settings
# TODO: These values are from Baytrail and need tuned for Rambi board
register "usb2_per_port_lane0" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
register "usb2_per_port_lane1" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
register "usb2_per_port_lane2" = "0x00049209"
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
device cpu_cluster 0 on
device lapic 0 on end
end