Since commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map") the ext-win-base and ext-win-size option has been
replaced with the "--mmap" option.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I33cfb59d9dbe88c4f618301ac1506e3281b1a483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
- Add step for building ifdtool (might not be obvious)
- Remove "./ifdtool COREBOOT_NAME" because it does nothing
- Add a small comment explaining what the -d and -x args do.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I868ea8918a1566cfade3bc161117f2ca8dfed31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85235
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The fsp_params.c file is refactored to move the debug message
control logic to a separate function, fsp_control_log_level().
This function takes an FSPM_UPD pointer and a boolean value
indicating whether debug messages should be enabled or disabled.
The fill_fsp_event_handler() function is updated to call
fsp_control_log_level() with the appropriate boolean value based on
the CONFIG(CONSOLE_SERIAL) and CONFIG(FSP_ENABLE_SERIAL_DEBUG)
Kconfig options.
BUG=b:227151510
TEST=Able to build and boot google/fatcat.
Change-Id: Ie2916ce82133058464d20eed327de7c7288e78a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85827
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit renames the Meteor lake Touch Controller device IDs to
include the supported bus/protocol for clarity. The IDs comes from
document #640228 - Meteor Lake External Design Specification volume 1.
Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85644
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't used anywhere, so remove it.
Change-Id: Ieb5980929ef35ae129f9e548da7ab71efa2ae7f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84594
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ASPM helper functions are the same for all Intel SOCs
since Skylake, so move them to common code.
Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:387056119
BRANCH=none
TEST=built firmware and verified by power team, and noise pass.
Change-Id: I11e1fae6d0b8508760090956ca6d77b012aa4bad
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85826
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Based on discussions on various patches (CB:57140), the idea was to
enable all bits to avoid incomplete ports.
Therefore, enable all bits - the same as ADL.
Change-Id: I5ace878faa09b959384338efcdbdfce390145002
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a null check around the usage of the RFWU (Retimer Firmware
Update path) in the `usb4_retimer_execute_ec_cmd` function. This
ensures that any interaction with RFWU is only performed when the
path is valid, preventing potential null pointer dereferences.
This fixes are large amount of errors when `ec_retimer_fw_update_path`
isn't declared, such as comparisons like `If ((Local0 == Break))`.
Change-Id: I5a219345440f91332f680885b51e2cc09f14f7a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
The current Pull-Down capabilities of the SPMI are insufficient and
require optimization. Configure the SCL and SDA of the SPMI-P to
Pull-Down mode on MT8196 SoC side. It is done only once during the SPMI
read check to fix SPMI clock calibration failure.
TEST=Build pass
BUG=b:361174333
Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85751
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8
"Other Device ID" specifies that the first Thunderbolt PCIe root port
number is 21.
The previous offset of 0x10, inherited from Meteor Lake code, caused
an issue that resulted in:
- Temporary deactivation of Thunderbolt PCI devices during ramstage
- Failure to generate critical ACPI SSDT power management data for the
port
This error led to instability in PCIe tunneling during power state
transitions.
Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85781
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since all USB configurations are read from the southbridge devicetree,
these configurations aren't used anymore.
TEST=Built Z220 CMT with BUILD_TIMELESS=1, output ROMs are identical.
Change-Id: I8f478625ad4928cf23bbb8ac2689004010bbdd4b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85817
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
There are several unused includes here.
TEST=Built 8200 usdt with BUILD_TIMELESS=1, no change in output ROM.
Change-Id: Ib4082a2589441b1d257db622380733e2825b27c2
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This change adds support for the generic LPC memory range configuration
in the EC ACPI code.
If CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled, the
EC will use the generic LPC memory range for EMEM related communication
between EC and AP Firmware. This is useful for platforms that do not
have a dedicated IO range like accessed EMEM through port 62/66 or
through LPC at 900h.
The generic LPC memory range is defined by the _SB.PCI0.LPCB.GLGM()
method. This method returns the base address and size of the memory
range.
Update the comment section to reflect the alternative source for EMEM
data when CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled.
BUG=b:354066052
TEST=Build and boot on a device with
CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled.
Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To improve boot time, raise little CPU from 700MHz to 2.4GHz at romstage
(before DRAM calibration).
FW logs:
Check CPU freq: 2400120 KHz
BUG=b:317009620
TEST=Build pass, boot ok.
Change-Id: I14a31f3a51ca246b842cc0ef740c43ff5d857310
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change adds the wake source for the touchpad on the
google/fatcat mainboard.
This allows the touchpad to wake the system from suspend.
BUG=b:274919134
TEST=Verified that the system can be woken up from suspend by tapping
the touchpad.
Change-Id: I6b265fb6b220cc779ea011e767ae98d4cf37e0d2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This change modifies the touchpad interrupt configuration to use
edge-triggered interrupts instead of level-triggered interrupts.
This is necessary to ensure that the touchpad interrupt is properly
detected by the AP w/o seeing interrupt flood.
BUG=b:376019577
TEST=Verified that the touchpad works smoothly with this change.
Change-Id: Ida0dfe10963a979c5e977133149d97799a76e3b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85802
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the power team’s recommendation:
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8
- Set FastPkgCRampDisable VCCIA and VCCGT to "true"
BUG=b:380384127
TEST=built firmware and verified by power team, and noise pass
Change-Id: Ib7f60f1248c6b46f4f9bac1731be4f0396766ae2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85798
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
has_power_resource is a boolean, so use true, false instead of 0, 1.
Change-Id: I25b86ef577e072cfe3ef5dc2447113f11c51f747
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Modify early pad configuration TPM bus from I2C3 to I2C1.
Francka TPM bus is I2C1.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: Id08575d28f6f3bced74c0b301756fc8239cfd190
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85736
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In MT8196, CKSYS achieves power efficiency by dynamically turning the
clocks on or off based on the status provided by PERI.
TEST=Build pass, boot log:
mtk_cksys_init = 0x1
BUG=b:317009620
Change-Id: I70f710f068d7d882037691930a90c83adaab15d2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The plan is to have a setup menu in edk2 to configure coreboot options
without having to describe the options in both coreboot and edk2; that
would be a maintenance nightmare. Options are passed to edk2 using CFR
structures, edk2 stores the values in the variable store in flash, and
coreboot reads the option values using the EFI variable store backend.
Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Fix some typos and also update the naming convention of
`CFR_OPTFLAG_GRAYOUT` to `CFR_OPTFLAG_INACTIVE` as per reviews.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id66808382b93e32c58024462c18b20c2a89d6d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Change the ram_id to 2 for MT62F2G32D4DS-020 WT:F based on the
hardware schematic MB_SCH_1224A.
BUG=b:372395010
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Ia486d892fca0ed2a9e3e869b97b43af617ef17ac
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85775
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case.
BUG=b:377798581
TEST=See power limit override log message when the battery is missing
on fatcat board
Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85146
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a new function,
google_chromeec_is_barrel_charger_present(), which checks if a barrel
charger is present.
The function uses the following logic to determine if a barrel charger
is present:
- If both a barrel charger and USB-C PD are present, then the barrel
charger takes precedence over USB-C PD. As a result,
google_chromeec_is_usb_pd_attached() will return false. This logic can
be used to deterministically say if a barrel charger is present even
when both a barrel charger and USB-C PD are attached.
- If an AC charger is detected and USB-C PD is not present, then a
barrel charger must be present.
This change allows the EC to accurately detect the presence of a barrel
charger, even when a USB-C PD charger is also attached.
BUG=b:377798581
TEST=Able to read the charger status correctly while booting
google/fatcat.
Experiment #1:
- USB-C PD Attached = yes
- Barrel Attached = No
- Charger Detected = Yes
```
fatcat-rev257 ~ # cbmem -c | grep -5 "ac_charger_present"
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: yes
[INFO ] baseboard_devtree_update: Barrel Absent
```
Experiment #2:
- USB-C PD Attached = No
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #3:
- USB-C PD Attached = Yes
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #4:
- USB-C PD Attached = No
- Barrel Attached = No
- Charger Detected = No
```
[INFO ] ac_charger_present: no
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Absent
```
Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch adds a new API `google_chromeec_is_below_critical_threshold()
` to check if the battery level is below the critical threshold.
The API uses the existing `ec_cmd_battery_get_dynamic()` command to
retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL`
flag to determine if the battery level is critical.
This API can be used by other components to query the battery critical
status and take necessary actions, for example, while the system is
booting with low battery fuel with and/or without an AC
charger attached.
This addresses the need to implement a low battery charger icon and
detect when the system is booting with low battery fuel. The existing
`google_chromeec_is_battery_present_and_above_critical_threshold()`
API is not suitable for this purpose because any negative decision
(like battery not present and/or battery is critically low) implemented
around this existing API will also render the lower battery indicator
when the system is booting into battery cut-off mode. Ideally, we do not
wish to render any icon and simply allow boot to the OS during system
battery cut-off boot.
BUG=b:377798581
TEST=Able to read the battery status correctly while booting
google/fatcat.
Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85759
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces a new API, `google_chromeec_is_charger_present()`,
to determine if a charger is connected.
The API leverages the existing `ec_cmd_battery_get_dynamic()` command
to retrieve battery flags and checks the `EC_BATT_FLAG_AC_PRESENT`
flag to ascertain charger presence.
Other components can leverage this API to query the charger status,
which is particularly useful for distinguishing between barrel chargers
and USB-C chargers after relying on the
`google_chromeec_is_usb_pd_attached()` API.
BUG=b:377798581
TEST=Able to read the charger status (w/ barrel and/or w/ USB-PD)
correctly while booting google/fatcat.
Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85758
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces a new API, `google_chromeec_is_usb_pd_attached()`
which checks the current status of the USB-C port and returns whether a
USB Power Delivery (PD) charger is currently connected.
This API is useful for determining if the system is currently being
powered by a PD charger.
BUG=b:377798581
TEST=Able to read the PD status correctly while booting google/fatcat.
Change-Id: I47c934ee8a7563d4ba5124bff5613e61dd66e923
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add MT6685 initial settings and ADC init settings to support Thermal
Information Acquisition (TIA). TIA will read thermal info in HW.
TEST=Build pass
BUG=b:317009620
Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85734
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Use the helper functions added to Alder Lake which will configure
ASPM and L1 Subsstate control based on Kconfig, but retain the
capability to override the specific levels from devicetree.
Change-Id: Ia5cc11188b245a93c303117589bd9d3c18c2877e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As Intel has provided fixes regarding CLKREQ pins issue with new
UPD settings as described in commit b8abde7a8e
("soc/intel/alderlake: Disable PCIe clock gating"), remove this
WA as introduced by this commit 586b1c8da0
("mb/prodrive/atlas: Add workaround for CLKREQ pins").
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icbab617428551accda66499b7c2a32b2fa8c1689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79021
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the interrupt GPIO for LPSS I2C based touchpad from GPP_F18
to GPP_A13 to match the current fatcat configuration.
BUG=b:376019577
TEST=Able to verify the touchpad functionality using 'THAT' touchpad
module.
Change-Id: I37a9d3aae67883f9eb4f47d76b4f48ac6ebb6d16
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85754
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix regression introduced in commit 177bb5e9b9
("soc/intel/xeon_sp: Revise IIO domain ACPI name encoding").
Ensure domain ACPI names in the DSDT are in sync with SSDT ACPI names.
Fixes PCI devices not discovered on socket 1-3.
TEST: Booted in ibm/sbp1 and found all PCI devices working, no errors
in dmesg are shown.
Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Disable stylus function based on hardware schematic diagram.Because the external environment is floating, EE requires setting GPIO output to be pulled high or low.
BUG=b:372506691
TEST=Local build successfully.
Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85738
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Those documents have been moved to the archive.
Previous URLs now point to the documentation hub.
Change-Id: Ibb478b56d02842dc05475235b0fe80ab6c4e7d04
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
