FSP-M UPDs are programmed according to the configuration (Kconfig and
device tree).
BUG=348678529
TEST=Memory is initialized successfully and hardware is programmed as
desired on Intel pantherlake reference board.
Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG
is used to select different sar table (index 0 to 3).
BUG=b:348678529
TEST=emerge-fatcat coreboot chromeos-bootimage
Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
As https://doc.coreboot.org/contributing/coding_style.html#typedefs
states: "In general, a pointer, or a struct that has elements that can
reasonably be directly accessed should never be a typedef". This
commit makes the Intel Panther Lake SoC code comply with this by using
explicitly `struct soc_intel_pantherlake_config' in the
soc/intel/pantherlake code as I have been suggested to for the
`fsp_params.c' files. The rule being the rule and consistency across
a project matters more than personal preferences.
The documentation lists five exceptions and none on them cover the use
of `config_t' instead `struct soc_intel_pantherlake' but I believe it
does not make the code better for the following three reasons:
1. It is repetitive, make the line longer and the code is in
soc/intel/pantherlake so obviously the config_t data structure is
the pantherlake soc configuration.
2. It makes re-usability from one generation to another unnecessarily
harder.
3. This config_t abstraction is required for and used by some common
block code anyway. Hence, we end-up with some code using `config_t'
and other using the final structure which break the consistency of
the code when the project in looked as a whole.
BUG=348678529
TEST=Google fatcat mainboard compiles
Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+
board, but all of them use the same PCB (with different components).
The four SATA ports on the mainboard are provided by an onboard ASMedia
ASM1064B PCIe-to-SATA bridge. Unlike other mainboards in the tree using
an ASMedia ASM1061 or ASM1062 PCIe-to-SATA bridge, the ODROID-H4+ comes
with a SPI flash chip for the ASM1064B and does not seem to have issues
regarding PCIe power management (e.g. ASPM) or unusable SATA AHCI mode.
The ODROID-H4 comes with a single 16 MiB SPI flash chip. The ODROID-H4+
and the ODROID-H4 Ultra feature Dual BIOS, consisting of another 16 MiB
SPI flash chip and a 3-pin header to select between them. The board can
be flashed internally or using a SOIC-8 clip, but the M.2 slot may need
to be empty for the clip to fit.
Working:
- DDR5 SO-DIMM slot
- All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller
- UART to emit spam
- All video outputs (FSP GOP only lights up one output at a time)
- All USB ports (on the Ethernet connectors and on EXT_HDR1)
- M.2 M connector (PCIe only)
- PCIe power management
- Ethernet NICs
- eMMC
- HD audio codec and display audio
- S3 suspend/resume
- SeaBIOS <current version>
- MrChromebox edk2 <current version>
- Super I/O HWM on Linux (using out-of-tree it87 kernel module)
- Booting Arch Linux from NVMe and SATA
- Booting Windows 10 from NVMe
Not working:
- PECI: undocumented protocol and undocumented Super I/O
- Resuming on Windows 10 BSODs with `VIDEO_TDR_FAILURE`
Untested:
- Fan curves: may need to lower the temperature limits a bit
Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Trulo ISH uses the MAIN FW loaded by the kernel driver. This commit
enables DRIVER_INTEL_ISH_HAS_MAIN_FW for trulo, which skips printing the
ISH BUP version.
BUG=b:360144613
TEST=Local build successful and tested on trulo by toggling the
config. enabling this config skips printing the ISH version in cbmem.
1. CONFIG enabled
```
trulo-rev1 ~ # cbmem -c | grep ISH
[INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin
```
2. CONFIG disabled
```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.36864
[INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin
```
Change-Id: Ifebd563ec8ddb0378e1215a90396687857f3f71d
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84494
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to
indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware.
The ISH MAIN firmware is located in rootfs, hence we no longer need to
store the ISH BUP version in the CSE partition.
When this config is enabled, fetching the ISH BUP version from the CSE
firmware partition is skipped.
BUG=b:360144613
TEST=Local build successful and tested on trulo by toggling the
config. Enabling this config skips printing the ISH version in cbmem.
Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This also updates the mainboards depending on it.
Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84376
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add default value in nissa and trulo devicetree.cb, ODM have to review
the board design to follow RDC#646929 Power Map requirement.
NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST='emerge-nissa coreboot chromeos-bootimage'
Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the AST 2600 native graphics init driver to have a working
UEFI firmware menu displayed over KVM.
Change-Id: I2961576077ed3286df080cd09ffe68d835d8c3e7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add support for AST2600 as found on Intel Archer City CRB by using
the code found on Linux's ast drm driver.
While on it do minor modifications found on the Linux drm driver
that also affect the other ast chips.
New log messages:
[INFO ] ASpeed AST2050: initializing video device
[INFO ] ast_detect_chip: VGA not enabled on entry, requesting chip POST
[INFO ] ast_detect_config_mode: Using P2A bridge for configuration
[INFO ] ast_detect_chip: AST 2600 detected
[INFO ] ast_detect_chip: Analog VGA only
[INFO ] ast_driver_load: dram MCLK=890316000 MHz type=3 bus_width=16 size=01000000
[ERROR] No header found
[INFO ] ast_select_mode: Failed to decode EDID
[DEBUG] Assuming VGA for KVM
[DEBUG] AST: Display has 1024px x 768px
[DEBUG] Using framebuffer 1024px x 768px pitch 4096 @ 32 BPP
[INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
[INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0x94000000
[INFO ] ASpeed high resolution framebuffer initialized
TEST: Booted on Intel/ArcherCity CRB and used the UEFI firmware menu
over KVM using native graphics init.
Change-Id: I3d2d58d493706673c1b2ba4953967b1641bd6395
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit drops tcss_d3_hot_disable chip config as FSP is not
exposing the same purpose UPD anymore starting with Panther Lake
SoC.
BUG=b:348678529
TEST=Build for fatcat
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Updating from commit id c5b8de86c:
2024-07-22 18:07:11 +0200 - (Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration)
to commit id 8fb91783f:
2024-08-23 14:45:12 +0200 - (Merge "fix(intel): add in missing ECC register" into integration)
This brings in 213 new commits.
Change-Id: Ib52672e949a8e57fafc1ee9ae965a752020932b2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The declarations describing interface functions between SoCs
and openSIL glue code are common for the stub and Genoa POC,
and likely with future SoC openSIL implementations. Therefore,
move these out of SoC-specific header files and into
vc/amd/opensil/opensil.h.
This change facilitates swapping out the stub for the actual
openSIL glue code.
Change-Id: Icc8783ddb868f9f0c4cd357245604313eadfe531
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84428
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When battery not present, increase PL4 limit from 9 to 40.
Get PL setting from internal thermal and power team.
AC+DC/DC:
PL1=15W
PL2=25W
PL4=114W
AC ONLY:
PL1=15W
PL2=25W
PL4=40W
BUG=b:355094551
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Confirm on lotso EVT board, as expected.
Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84202
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We use ALC256 as HDA codec on fatcat hence, added the verb table.
BUG=b:348678529
TEST=Tested audio playback using HDA ALC256 codec on PTL reference
board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:348678529
TEST=Memory training is successful on google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit updates the fatcat mainboard to use the Panther Lake SoC
instead of Meteor Lake.
The changes include:
- Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option.
- Updating the `mainboard_update_soc_chip_config()` function to use the
`soc_intel_pantherlake_config` struct.
- Updating the devicetree to use the `soc/intel/pantherlake` chip.
- Updating variant header files to reflect the SoC change.
This update enables support for the Panther Lake SoC and its
features on the fatcat mainboard.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the virtual GPIOs for recovery and write protection
from the fatcat variant.
These GPIOs are not utilized on the fatcat platform, and their removal
simplifies the GPIO configuration and improves code readability.
The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther
Lake SoCs. Future changes will introduce a suitable GPIO device name
that meets the requirements of Panther Lake.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the SOC_INTEL_COMMON_BASECODE_RAMTOP Kconfig option for the
google/vell mainboard. This option ensures improving the boot time
on google/vell by 40ms in an average.
BUG=b:352330495
TEST=Able to reduced google/vell boot time by 40ms.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iedfd346c62b1ac79796042dd3569d846007b8f10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
When compiling with the C23 standard, bool, true, and false are
pre-defined by the language, so defining them in stdbool.h isn't allowed.
This fixes the following error:
src/include/stdbool.h:6:17: error: two or more data types in declaration specifiers
6 | typedef _Bool bool;
| ^~~~
src/include/stdbool.h:6:1: error: useless type name in empty declaration [-Werror]
6 | typedef _Bool bool;
| ^~~~~~~
Change-Id: Iec9b4e3f308008ece773ce3460daff97370161ea
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
"enable_c6dram" needs only 2 "states" to be clearly defined.
C provides "true/false", so use it instead of using unsigned int.
Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84155
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.
Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IBL eSPI should be correctly configured by LPC driver so that console
input is usable.
Change-Id: I77cc6dd67b36035974e7f268d32b8473e8d83483
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Work around a GCC LTO bug. Even if no buffer overflow is bound to happen
as the soldered down path is taken GCC LTO complains about this.
Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Deku S0ix is blocked by the SSD. Enable RTD3 for the SSD to unblock
S0ix. RTD3 for SSDs has already been enabled on Rex and Screebo, too.
To prevent this S0ix blocking issue, RTD3 should also be enabled for
Karis.
BUG=361011799
TEST=Run suspend_stress_test and check whether DUT can enter S0iX.
suspend_stress_test w/o this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Suspend failed, s0ix count did not increment from 19182060
Substate Residency
S0i2.0 0
S0i2.1 0
S0i2.2 0
And PC10 residency is only 60% (by SoCWatch)
suspend_stress_test w/ this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Substate Residency
S0i2.0 0
S0i2.1 19186
S0i2.2 3389654
And PC10 residency is ~90% (by SoCWatch)
Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as vell is using a converged firmware image.
This effort also helps to save vell boot time by 80-100ms as RPL FSP is
better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves
10ms of the boot time.
BUG=b:352330495
TEST=Able to build and boot google/vell.
warm reboot time w/o this CL
```
Total Time: 1,408,669
```
warm reboot time w/ this CL
```
Total Time: 1,235,651
```
Change-Id: I8f7dd76f00cfeff2908aeb805524706ac23403fa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84491
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables unused I2C6 controller for the 'vell' variant of
the 'brya' mainboard.
BUG=b:352330495
TEST=Able to build and boot google/vell.
Change-Id: I5b39e44bb64bf2285c962249c0d94a8d5325f0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the kanix variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:368501705
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KANIX
Change-Id: Id74a084ed3cebb65625166e3098f43e41a63f5f9
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Earlier change (https://review.coreboot.org/c/coreboot/+/84019)
pushed to resolve the privacy LED blinking issue regressed the camera
autofocus functionality. This change updates the power resource for
NVM and VCM in line with the tivviks schematics to fix the issue.
BUG=b:365899407
TEST=Build and boot tivviks. Verified the Autofocus and all the
camera basic sanity tests.
Change-Id: Id3e256d59982ac176844e289f18ee450079704b9
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Compared to MT8186, MT8186T requires initializing the PMIC MT6319 in the DTS file, which necessitates using different SKU ID to distinguish between the MT8186 and MT8186T.
For MT8186, factory pre-flashed 0x7fffffff as unprovisioned SKU ID and
kernel can use the corresponding DTS file. To make MT8186T functional
on unprovisioned devices, change the SKU ID to 0x7ffffeff, so that the
correct DTS file will be selected by the payload.
BUG=b:365730137
TEST=1. Pre-flashed 0x7fffffff and boot OS.
2. Check OS boot normally by 0x7ffffeff.
BRANCH=corsola
Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84342
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I6012fd948b4350bda7af5390badac737553fa872
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84430
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
