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mb/google/rex/{deku,karis}: Enable RTD3 for SSD

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Deku S0ix is blocked by the SSD. Enable RTD3 for the SSD to unblock
S0ix. RTD3 for SSDs has already been enabled on Rex and Screebo, too.
To prevent this S0ix blocking issue, RTD3 should also be enabled for
Karis.

BUG=361011799
TEST=Run suspend_stress_test and check whether DUT can enter S0iX.

suspend_stress_test w/o this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
    Suspend failed, s0ix count did not increment from 19182060
    Substate   Residency
    S0i2.0     0
    S0i2.1     0
    S0i2.2     0
    And PC10 residency is only 60% (by SoCWatch)

suspend_stress_test w/ this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
    Substate   Residency
    S0i2.0     0
    S0i2.1     19186
    S0i2.2     3389654
    And PC10 residency is ~90% (by SoCWatch)

Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Curtis Chen 2024-09-21 12:51:43 +08:00 • committed by Subrata Banik
commit 735ca7f24a
2 changed files with 14 additions and 0 deletions
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7
src/mainboard/google/rex/variants/deku/overridetree.cb
View file

@ -167,6 +167,13 @@ chip soc/intel/meteorlake
.clk_req = 7,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
register "srcclk_pin" = "7"
device generic 0 on end
end
end # PCIE11 SSD card
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end

7
src/mainboard/google/rex/variants/karis/overridetree.cb
View file

@ -265,6 +265,13 @@ chip soc/intel/meteorlake
.clk_req = 8,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
register "srcclk_pin" = "8"
device generic 0 on end
end
end # PCIE10 SSD card
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp2 on end