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mb/google/{nissa,trulo}: Add Vccin Aux Imon Iccmax default value

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Add default value in nissa and trulo devicetree.cb, ODM have to review
the board design to follow RDC#646929 Power Map requirement.

NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL.

BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST='emerge-nissa coreboot chromeos-bootimage'

Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Simon Yang 2024-08-01 18:51:32 +08:00 • committed by Subrata Banik
commit 9bd0ca2f5e
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
View file

@ -94,6 +94,9 @@ chip soc/intel/alderlake
# Disable Package C-state demotion for nissa baseboard.
register "disable_package_c_state_demotion" = "true"
# Vccin Aux Imon Iccmax, follow RDC#646929 Power Map requirement
register "vccin_aux_imon_iccmax" = "PD_TIER_VOLUME" # 27A
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |

3
src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
View file

@ -44,6 +44,9 @@ chip soc/intel/alderlake
register "pch_hda_sdi_enable[0]" = "true"
register "pch_hda_sdi_enable[1]" = "true"
# Vccin Aux Imon Iccmax, follow RDC#646929 Power Map requirement
register "vccin_aux_imon_iccmax" = "PD_TIER_VOLUME" # 27A
device domain 0 on
# The timing values can be derived from datasheet of display panel
# You can use EDID string to identify the type of display on the board