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soc/intel/ptl: Remove tcss_d3_hot_disable en config structure field

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This commit drops tcss_d3_hot_disable chip config as FSP is not
exposing the same purpose UPD anymore starting with Panther Lake
SoC.

BUG=b:348678529
TEST=Build for fatcat

Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This commit is contained in:
Jeremy Compostella 2024-09-20 12:13:11 -07:00 • committed by Subrata Banik
commit 1005e49580
1 changed files with 0 additions and 2 deletions
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2
src/soc/intel/pantherlake/chip.h
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@ -172,8 +172,6 @@ struct soc_intel_pantherlake_config {
/* Enable S0iX support */
bool s0ix_enable;
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
bool tcss_d3_hot_disable;
/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
bool tcss_d3_cold_disable;
/* Enable DPTF support */